基于FPGA的混合内存仿真系统
FPGA-based Hyrbid Memory Emulation System
AI总结：
针对混合内存系统设计探索中仿真速度慢的问题，提出基于FPGA的仿真平台，利用硬IP ARM处理器加速，相比Gem5实现9280倍仿真加速。
摘要：
混合内存系统由新兴的非易失性存储器（NVM）和DRAM组成，已被提出以应对应用程序日益增长的内存需求。新兴的NVM技术，如相变存储器（PCM）、忆阻器和3D XPoint，具有更高的容量密度、极低的静态功耗和更低的每GB成本。然而，与DRAM相比，NVM具有更长的访问延迟和有限的写入耐久性。两类内存的不同特性指向了包含多种主内存类别的混合内存系统的设计。\n在新架构的迭代和增量开发中，仿真完成的及时性对项目进展至关重要。因此，需要一种高效的仿真方法来评估不同混合内存系统设计的性能。混合内存系统的设计探索具有挑战性，因为它需要仿真完整的系统栈，包括操作系统、内存控制器和互连。此外，用于内存性能测试的基准应用程序通常具有更大的工作集，因此需要更长的仿真预热期。\n在本文中，我们提出了一种基于FPGA的混合内存系统仿真平台。我们针对移动计算系统，该系统对能耗敏感，并且可能因其功耗效率而采用NVM。这里，由于我们平台的重点是混合内存系统的设计，我们利用板载硬IP ARM处理器来提高仿真性能，同时提高结果的准确性。因此，用户可以使用FPGA逻辑元件实现其数据放置/迁移策略，并快速有效地评估新设计。结果表明，与软件对应物Gem5相比，我们的仿真平台在仿真时间上提供了9280倍的加速。
英文摘要：
Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of applications. Emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of two memory classes point towards the design of hybrid memory systems containing multiple classes of main memory. In the iterative and incremental development of new architectures, the timeliness of simulation completion is critical to project progression. Hence, a highly efficient simulation method is needed to evaluate the performance of different hybrid memory system designs. Design exploration for hybrid memory systems is challenging, because it requires emulation of the full system stack, including the OS, memory controller, and interconnect. Moreover, benchmark applications for memory performance test typically have much larger working sets, thus taking even longer simulation warm-up period. In this paper, we propose a FPGA-based hybrid memory system emulation platform. We target at the mobile computing system, which is sensitive to energy consumption and is likely to adopt NVM for its power efficiency. Here, because the focus of our platform is on the design of the hybrid memory system, we leverage the on-board hard IP ARM processors to both improve simulation performance while improving accuracy of the results. Thus, users can implement their data placement/migration policies with the FPGA logic elements and evaluate new designs quickly and effectively. Results show that our emulation platform provides a speedup of 9280x in simulation time compared to the software counterpart Gem5.
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