ControlPULP：一款面向众核HPC处理器、基于FPGA硬件在环功率与热仿真的RISC-V片上并行功率控制器
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
AI总结：
本文提出ControlPULP，一个基于RISC-V的开源并行功率控制器平台，通过多核集群加速实时功率管理策略，在72核HPC处理器用例中实现4.9倍加速和DVFS跟踪偏差小于3% TDP。
摘要：
高性能计算（HPC）处理器如今是集成的信息物理系统，需要复杂且高带宽的闭环功率与热控制策略。为了高效满足实时多输入多输出（MIMO）最优功率需求，高端处理器集成了片上功率控制器系统（PCS）。传统PCS基于简单的微控制器（MCU）级核心，而为了管理不断增加的核数、功率状态以及工艺、电压和温度波动，需要更具可扩展性和灵活性的PCS架构来支持先进的MIMO控制算法。本文提出了ControlPULP，一个开源的、硬件/软件协同的RISC-V并行PCS平台，由一个具有快速中断处理的单核MCU、一个可扩展的多核可编程集群加速器以及一个专用DMA引擎组成，用于并行加速实时功率管理策略。ControlPULP依赖FreeRTOS来调度一个反应式功率控制固件（PCF）应用层。我们在一个面向下一代72核HPC处理器的功率管理用例中演示了ControlPULP。我们首先表明，多核集群加速了PCF，与单核执行相比实现了4.9倍的加速，从而在控制超周期内支持更先进的功率管理算法，且面积开销很小，约为现代HPC CPU裸片面积的0.1%。然后，我们通过设计一个基于FPGA的闭环仿真框架来评估PCS和PCF，该框架利用异构SoC范式，相对于软件等效的模型在环方法，实现了DVFS跟踪，其平均偏差在受控对象热设计功耗（TDP）的3%以内。最后，我们表明，在计算密集型工作负载下，所提出的PCF与工业级控制算法相比具有优势。
英文摘要：
High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant's thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads.
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