比较三进制和二进制加法器和乘法器
Comparing ternary and binary adders and multipliers
摘要：
虽然许多论文提出了三进制加法器和三进制乘法器的实现，但通常没有与相应的二进制加法器和乘法器进行比较。本文以1-bit和1-trit加法器和1-bit和1-trit乘法器为基本模块，比较了具有相同运算能力的二进制和三进制加法器和乘法器的实现。然后，我们通过使用相同的CNTFET技术来比较这些基本块的复杂度，以评估一侧的N位加法器和M-trit加法器以及N × N位乘法器和M × M trit乘法器的总体复杂度，其中M = N/IR（IR = log（3）/log（2）是信息比）。虽然三进制加法器和乘法器具有较少的输入和输出连接并且使用较少的基本构建块，但是三进制构建块的复杂度太高并且三进制加法器和乘法器不能与二进制加法器和乘法器竞争。
英文摘要：
While many papers have proposed implementations of ternary adders and ternary multipliers, no comparisons have generally been done with the corresponding binary ones. We compare the implementations of binary and ternary adders and multipliers with the same computing capability according to the basic blocks that are 1-bit and 1-trit adders and 1-bit and 1-trit multipliers. Then we compare the complexity of these basic blocks by using the same CNTFET technology to evaluate the overall complexity of N-bit adders and M-trit adders on one side, and NxN bit multipliers and MxM trits multipliers with M = N/IR (IR = log(3)/log(2) is the information ratio). While ternary adders and multipliers have less input and output connections and use less basic building blocks, the complexity of the ternary building blocks is too high and the ternary adders and multipliers cannot compete with the binary ones.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
