单个DSP块上多重乘法的近精确参数逼近
Near-Precise Parameter Approximation for Multiple Multiplications on A Single DSP Block
摘要：
乘法累加（MAC）运算是DSP应用的主要计算单元。DSP块是在FPGA中实现MAC的有效解决方案之一。然而，由于DSP块具有宽乘法器和加法器块，因此使用低位长参数的MAC操作导致利用不足的问题。因此，引入了一种有效的近似技术。该技术包括基于单DSP -多乘法（SDMM）执行的低位长定点参数的操纵和近似。SDMM通过分离乘法和累加操作改变了DSP块中的传统MAC实现。虽然DSP块中可用的累加器硬件用于多参数乘法，但并行LUT用于MAC运算的累加部分。使用Alexnet和VGG-16网络以及Tiny ImageNet数据集，针对不同的CNN权重位精度评估了所开发的优化技术的准确性。在几乎所有情况下，优化可以在不损失精度的情况下实现，而在少数情况下会导致轻微的精度损失。通过这些优化，SDMM是在一个小的硬件开销的代价。例如，单个DSP块执行3个8位定点参数乘法。由于我们的优化，参数在片外存储器中以不同的格式表示，提供高达33%的压缩，而无需任何硬件成本。当与VGG-16的其他压缩方法结合使用时，压缩率可进一步提高高达97%。达到此压缩率需要额外的硬件成本。一个原型脉动阵列架构，采用我们的优化Xilinx Zynq FPGA上实现。对于8位、6位和4位输入变量，它分别将DSP块的数量减少了66.6%、75%和83.3%。
英文摘要：
A multiply-accumulate (MAC) operation is the main computation unit for DSP applications. DSP blocks are one of the efficient solutions to implement MACs in FPGA's. However, since the DSP blocks have wide multiplier and adder blocks, MAC operations using low bit-length parameters lead to an underutilization problem. Hence, an efficient approximation technique is introduced. The technique includes manipulation and approximation of the low bit-length fixed-point parameters based upon a Single DSP - Multiple Multiplication (SDMM) execution. The SDMM changes the traditional MAC implementation in the DSP block by separating multiplication and accumulation operations. While the accumulator hardware available in the DSP block is used for multiple parameter multiplication, parallel LUTs are employed for the accumulation part of the MAC operation. The accuracy of the developed optimization technique was evaluated for different CNN weight bit precisions using the Alexnet and VGG-16 networks and the Tiny ImageNet dataset. The optimization can be implemented without loss of accuracy in almost all cases, while it causes slight accuracy losses in a few cases. Through these optimizations, the SDMM is performed at the cost of a small hardware overhead. For example, a single DSP block executes 3 8-bit fixed-point parameter multiplications. As a result of our optimizations, the parameters are represented in a different format on off-chip memory, providing up to 33% compression without any hardware cost. The compression rate can be further increased by up to 97% when used in conjunction with other compression methods for the VGG-16. Reaching this compression rate requires extra hardware cost. A prototype systolic array architecture was implemented employing our optimizations on a Xilinx Zynq FPGA. It reduced the number of DSP blocks by 66.6%, 75%, and 83.3% for 8, 6, and 4-bit input variables, respectively.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
