从Web生成和验证自定义乘法IP块
Generation and Validation of Custom Multiplication IP Blocks from the Web
摘要：
每个CPU都有一个或多个算术和逻辑单元。由这些单元执行的一个流行操作是乘法。自动生成用于执行此操作的自定义VHDL模型，允许设计人员实现时间有效的设计空间探索。虽然这些单元在现代数字电路和DSP中得到了大量利用，但没有工具可以从Web访问，以生成任意和不同输入位宽的此类设计的HDL描述。在本文中，我们提出了我们的Web访问工具，以构建完全定制的优化乘法单元，以及随机生成的测试向量，用于验证。我们的新型工具是第一个基于Web的EDA工具之一，可以自动化此类单元的设计，同时提供自定义测试台来验证其正确性。我们在Xilinx Virtex 6 FPGA上的合成电路，工作频率高达589 MHz。
英文摘要：
Every CPU carries one or more arithmetical and logical units. One popular operation that is performed by these units is multiplication. Automatic generation of custom VHDL models for performing this operation, allows the designer to achieve a time efficient design space exploration. Although these units are heavily utilized in modern digital circuits and DSP, there is no tool, accessible from the web, to generate the HDL description of such designs for arbitrary and different input bitwidths. In this paper, we present our web accessible tool to construct completely custom optimized multiplication units together with random generated test vectors for their verification. Our novel tool is one of the firsts web based EDA tools to automate the design of such units and simultaneously provide custom testbenches to verify their correctness. Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to 589 Mhz.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
