电子器件的主要目标是实现低功耗、高速度与紧凑面积。超大规模集成（VLSI）器件的性能受算术运算影响，其中乘法是核心运算。因此，高速乘法器对开发任意信号处理模块都至关重要。现有文献已对大量乘法器进行了研究，其速度很大程度上取决于部分积（PPs）的累加方式。为了突破现有方法的乘法速度上限，本文提出了一种基于近似加法器的乘法器。该方法采用新型近似加法器，可同时对来自两个连续位的部分积进行相加。所提出的乘法器被应用于均值滤波器结构中，使用VHDL在ISE Design Suite 14.7中完成设计，并在Xilinx Spartan3-XC3S400 FPGA开发板上综合实现。与文献中的方案相比，该乘法器的功耗和功耗-延迟积（PDP）分别降低了56.09%和73.02%。通过均值滤波器系统验证了所提乘法器的有效性，结果显示其可节省33.33%的功耗。此外，该乘法器的峰值信噪比（PSNR）提升30.58%、结构相似性指数（SSIM）提升22.22%，精度优于其他近似乘法器，同时功耗处于较低水平。
英文摘要：
Electronic devices primarily aim to offer low power consumption, high speed, and a compact area. The performance of very large-scale integration (VLSI) devices is influenced by arithmetic operations, where multiplication is a crucial operation. Therefore, a high-speed multiplier is essential for developing any signal-processing module. Numerous multipliers have been reviewed in existing literature, and their speed is largely determined by how partial products (PPs) are accumulated. To enhance the speed of multiplication beyond current methods, an approximate adder-based multiplier is introduced. This approach allows for the simultaneous addition of PPs from two consecutive bits using a novel approximate adder. The proposed multiplier is utilized in a mean filter structure and implemented in ISE Design Suite 14.7 using VHDL and synthesized on the Xilinx Spartan3-XC3S400 FPGA board. Compared to the literature, the proposed multiplier achieves power and power-delay product (PDP) improvements of 56.09% and 73.02%, respectively. The validity of the expressed multiplier is demonstrated through the mean filter system. Results show that it achieves power savings of 33.33%. Additionally, the proposed multiplier provides more accurate results than other approximate multipliers by expressing higher values of peak signal-to-noise ratio (PSNR), (30.58%), and structural similarity index metric (SSIM), (22.22%), while power consumption is in a low range.
Dynamic Ultrasound Beamforming Using Left-to-Right Arithmetic Adders on FPGA
Faculty of Informatics and Data Science, University of Regensburg（雷根斯堡大学信息科学与数据科学学院）；Department of Computer Engineering, College of Computing and Mathematics, KFUPM（阿卜杜拉国王科技大学计算机工程学院计算与数学学院）
AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence
Noah’s Ark Lab, Huawei Technologies（华为技术有限公司诺亚方舟实验室）；Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences（中国科学院深圳先进技术研究院）；the University of Sydney（悉尼大学）
A Digital Hardware Fast Algorithm and FPGA-based Prototype for a Novel 16-point Approximate DCT for Image Compression Applications
离散余弦变换（DCT）是许多图像和视频编码标准中的关键步骤。8点DCT是一个重要的特殊情况，拥有几个低复杂度的近似广泛研究。然而，16点DCT变换具有能量压缩优势。在这个意义上，本文提出了一种新的16点DCT近似与零乘法复杂度。所提出的变换矩阵是正交的，只包含0和1。所提出的变换优于众所周知的沃尔什-哈达玛变换和当前最先进的16点近似。文中还介绍了一种快速的变换算法。这种快速算法的实验验证使用硬件实现，物理上实现和验证的40纳米CMOS Xilinx Virtex-6 XC 6VLX 240 T FPGA芯片的最大时钟速率为342 MHz。与文献[S.布格泽尔湾O. Ahmad和M. N. S.斯瓦米一种新的图像压缩变换。在{ \em Proceedings of the 53rd IEEE International Midwest Symposium on Circuits and Systems（MWSCAS）}，2010]中。
CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation
Electrical and Computer Engineering Iowa State University of Science and Technology（电气与计算机工程学院爱荷华州立大学科学与技术学院）；Electrical and Computer Engineering University of Minnesota Twin Cities（电气与计算机工程学院明尼苏达大学双城分校）
