比较四进制和二进制乘法器
Comparing quaternary and binary multipliers
摘要：
我们比较了一个8 × 8位乘法器的实现与两个不同的4 × 4四进制数字乘法器的实现。将该二进制乘法器与四进制到二进制解码器和二进制到四进制编码器接口导致4x4乘法器优于4x4四进制乘法器的最佳直接实现。与二进制1位乘法器和全加器相比，在该直接实现中使用的1位乘法器和1位加法器的更大复杂性不能通过减少的四进制运算符的计数来补偿。由于最好的四进制乘法器包括相应的二进制乘法器，这意味着没有机会获得更少的互连，更小的芯片面积，更低的功耗与四进制乘法器。
英文摘要：
We compare the implementation of a 8x8 bit multiplier with two different implementations of a 4x4 quaternary digit multiplier. Interfacing this binary multiplier with quaternary to binary decoders and binary to quaternary encoders leads to a 4x4 multiplier that outperforms the best direct implementation of a 4x4 quaternary multiplier. The far greater complexity of the 1-digit multipliers and 1-digit adders used in this direct implementation compared to the binary 1-bit multipliers and full adders cannot be compensated by the reduced count of quaternary operators. As the best quaternary multiplier includes the corresponding binary one, it means that there is no opportunity to get less interconnects, less chip area, less power dissipation with the quaternary multiplier.
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