Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High dielectric constant (High-\k{appa}/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously. To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm2) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability (σΔVth). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.
Contact-Barrier Free, High Mobility, Dual-Gated Junctionless Transistor Using Tellurium Nanowire
栅环纳米线晶体管由于其极强的静电控制和垂直集成能力，是一个非常有前途的候选人亚5纳米技术节点。特别地，由于避免了通过离子注入形成陡峭的源极/漏极结，无结纳米线晶体管是高度可缩放的，具有降低的可变性。在这里，我们展示了一个双栅无结纳米线\emph{p}型场效应晶体管使用碲纳米线作为沟道。由于纳米线的独特的螺旋晶体结构，加上悬挂键的自由，高品质的hBN栅极电介质的集成的悬挂键自由的表面，使我们能够实现在270 K的$570\,\mathrm{cm^{2}/V\cdot s}$的声子限制的场效应空穴迁移率，这是远远高于国家的最先进的应变硅空穴迁移率。通过降低温度，迁移率增加到$1390\,\mathrm{cm^{2}/V\cdot s}$，并且主要受到库仑散射的限制。\txc{The combination of an electron affinity of $\sim$4 eV and a small bandgap of tellurium provides zero Schottky barrier height for hole injection at the metal-contact interface}，其对于在高度缩放的晶体管中减小接触电阻是显著的。利用这些属性，再加上双栅极操作，我们实现了$216\,\mathrm{μA/μm}$的高驱动电流，同时保持超过$2\ti…
