Skybridge：替代CMOS的三维集成电路技术
Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS
摘要：
CMOS的持续缩放是集成电路（IC）小型化的主要催化剂，对全球社会经济进步至关重要。然而，随着MOSFET达到其基本极限，互连瓶颈正在主导IC的工作功率和性能，扩展到20 nm以下的技术被证明是具有挑战性的。迁移到3-D，作为一种推进扩展的方式，由于CMOS中与3-D组织不兼容的固有定制和制造要求，我们一直无法实现。部分尝试的芯片-芯片和层-层堆叠有其自身的局限性。我们提出了一种三维集成电路结构技术，天桥[TM]，它提供了技术缩放以及设计的范式转变。我们以统一的3D模板为基础，以3D结构为中心，共同构建Skybridge的核心方面，从器件到电路样式、连接性、热管理和制造路径。我们广泛的自下而上的模拟，考虑到详细的材料系统结构，制造工艺，器件和电路寄生效应，对包括设计的微处理器在内的几种设计进行了模拟，结果显示，与缩放的16 nm CMOS相比，密度为30- 60倍，性能为3.5倍，互连长度减少了10倍。制造级的热提取功能，成功地管理IC的3-D的热配置文件。Skybridge可以在21世纪提供超越CMOS的集成电路的连续缩放。
英文摘要：
Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.
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