基于混合CMOS-CNFET的NP动态超前进位加法器
Hybrid CMOS-CNFET based NP dynamic Carry Look Ahead Adder
摘要：
先进的电子器件技术要求更快的操作和更小的平均功耗，这是超大规模集成电路设计中最重要的参数。传统的互补金属氧化物半导体（CMOS）技术在器件的尺寸缩小中受到阈值电压和亚阈值泄漏问题的限制。这导致无法使其适应亚微米和纳米技术。碳纳米管（CNT）技术克服了阈值电压和亚阈值泄漏问题，尽管尺寸减小。基于CNT的技术开发了新兴技术中最有前途的器件，因为它具有大多数所需的功能。碳纳米管场效应晶体管（CNFET）是一种新型器件，有望在提高晶体管性能的同时保持晶体管的可扩展性。最近，CNT技术在纳米电子学应用中取得了巨大的进步。与硅基技术相比，CNFET避免了大多数基本限制，并提供了几个优势。虽然CNT作为一个更好的选择来克服一些大规模CMOS问题，CNT本身仍然沉浸在挫折中。在单个衬底上制作非常大的数字电路的碳纳米管是很难实现的。因此，采用p-CNFET和n-MOS晶体管设计了一种混合NP动态超前进位加法器（CLA）。在这里，CLA的性能进行了评估，在8位，16位，32位和64位的阶段与以下四个不同的实现：硅MOSFET（Si-MOSFET）多米诺逻辑，Si-MOSFET NP动态CMOS，碳纳米管MOSFET（CN-MOSFET）多米诺逻辑，和CN-MOSFET NP动态CMOS。最后，基于HSPICE仿真，在32 nm工艺下，对一种基于混合CMOS-CNFET的64位NP动态CLA进行了评估，该CLA在不增加传播延迟的情况下，有效地抑制了功耗。
英文摘要：
Advanced electronic device technologies require a faster operation and smaller average power consumption, which are the most important parameters in very large scale integrated circuit design. The conventional Complementary Metal-Oxide Semiconductor (CMOS) technology is limited by the threshold voltage and subthreshold leakage problems in scaling of devices. This leads to failure in adapting it to sub-micron and nanotechnologies. The carbon nanotube (CNT) technology overcomes the threshold voltage and subthreshold leakage problems despite reduction in size. The CNT based technology develops the most promising devices among emerging technologies because it has most of the desired features. Carbon Nanotube Field Effect Transistors (CNFETs) are the novel devices that are expected to sustain the transistor scalability while increasing its performance. Recently, there have been tremendous advances in CNT technology for nanoelectronics applications. CNFETs avoid most of the fundamental limitations and offer several advantages compared to silicon-based technology. Though CNT evolves as a better option to overcome some of the bulk CMOS problems, the CNT itself still immersed with setbacks. The fabrication of carbon nanotube at very large digital circuits on a single substrate is difficult to achieve. Therefore, a hybrid NP dynamic Carry Look Ahead Adder (CLA) is designed using p-CNFET and n-MOS transistors. Here, the performance of CLA is evaluated in 8-bit, 16-bit, 32-bit and 64-bit stages with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MOSFET (CN-MOSFET) domino logic, and CN-MOSFET NP dynamic CMOS. Finally, a Hybrid CMOS-CNFET based 64-bit NP dynamic CLA is evaluated based on HSPICE simulation in 32nm technology, which effectively suppresses power dissipation without an increase in propagation delay.
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