用于概率推理引擎的自相似磁电纳米电路技术
Self-similar Magneto-electric Nanocircuit Technology for Probabilistic Inference Engines
AI总结：
针对传统CMOS系统难以高效处理大规模概率图模型推理的问题，提出基于S-MTJ器件的磁电概率技术框架，实现概率直接计算与持久化存内计算，在贝叶斯似然估计上较45nm CMOS实现大幅降低面积、功耗与延迟。
摘要：
概率图模型是用于机器学习和不确定性推理的强大数学形式体系，被广泛应用于认知计算。然而，由于CMOS实现中的抽象层以及逻辑与内存分离导致的低效性，这类模型无法在传统系统上高效应用于大规模问题（变量规模约10万及以上）。本文提出了一种用于实现概率推理功能的磁电概率技术框架。该技术在新型混合信号电路框架中利用应变电子磁隧穿结（S-MTJ）器件，直接对概率进行计算，同时支持具备持久性的存内计算。对贝叶斯网络推理过程中的贝叶斯似然估计运算的初步评估显示，与等效的45nm CMOS布尔实现相比，该方案面积降低达127倍，有功功率降低达214倍，延迟降低达70倍。
英文摘要：
Probabilistic graphical models are powerful mathematical formalisms for machine learning and reasoning under uncertainty that are widely used for cognitive computing. However they cannot be employed efficiently for large problems (with variables in the order of 100K or larger) on conventional systems, due to inefficiencies resulting from layers of abstraction and separation of logic and memory in CMOS implementations. In this paper, we present a magneto-electric probabilistic technology framework for implementing probabilistic reasoning functions. The technology leverages Straintronic Magneto-Tunneling Junction (S-MTJ) devices in a novel mixed-signal circuit framework for direct computations on probabilities while enabling in-memory computations with persistence. Initial evaluations of the Bayesian likelihood estimation operation occurring during Bayesian Network inference indicate up to 127x lower area, 214x lower active power, and 70x lower latency compared to an equivalent 45nm CMOS Boolean implementation.
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