CMOS 2.0 -- 重新定义缩放的未来
CMOS 2.0 -- Redefining the Future of Scaling
AI总结：
CMOS 2.0通过3D堆叠异构主动器件层，重新定义未来缩放方向，提升性能、面积和成本效益。
摘要：
我们提出通过利用先进芯片制造中的两个最新发展，即3D晶圆键合和背面处理，重新审视功能缩放范式。这种方法导致提出CMOS 2.0平台。主要思想是将CMOS路线图从几何缩放转向细粒度异构3D堆叠的专用主动器件层，以实现未来技术世代预期的终极功率-性能-面积和成本收益。然而，此类平台的高效利用需要设计能够最佳映射到该技术的架构，以及支持它的EDA基础设施。我们还讨论了可靠性问题及最终的缓解方法。本文为未来CMOS 2.0系统设计中的主要颠覆提供了指引。
英文摘要：
We propose to revisit the functional scaling paradigm by capitalizing on two recent developments in advanced chip manufacturing, namely 3D wafer bonding and backside processing. This approach leads to the proposal of the CMOS 2.0 platform. The main idea is to shift the CMOS roadmap from geometric scaling to fine-grain heterogeneous 3D stacking of specialized active device layers to achieve the ultimate Power-Performance-Area and Cost gains expected from future technology generations. However, the efficient utilization of such a platform requires devising architectures that can optimally map onto this technology, as well as the EDA infrastructure that supports it. We also discuss reliability concerns and eventual mitigation approaches. This paper provides pointers into the major disruptions we expect in the design of systems in CMOS 2.0 moving forward.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
