超导加速器的实例
A Case for Superconducting Accelerators
摘要：
随着传统CMOS技术的扩展速度放缓，人们对能够提高性能或能效的替代技术的兴趣越来越大。基于约瑟夫森结（JJ）的超导电路是一种新兴的技术，它可以提供可以在皮秒量级上进行开关的器件，并且与CMOS相比，其开关能量低两个数量级。虽然基于JJ的电路可以提供高工作频率和能效，但该技术面临三个关键挑战：有限的器件密度和缺乏用于存储器结构的面积高效技术，与CMOS相比减少的栅极扇出，以及由于操作环境而发生的新的磁通陷阱故障模式。由于缺乏高密度存储器技术，超导技术在短期内的应用领域，具有高的计算强度，但需要微不足道的内存量限制。在本文中，我们研究了使用超导技术为比特币挖矿应用中常用的SHA-256引擎构建加速器。我们表明，仅仅将现有的基于CMOS的加速器移植到超导技术上，就可以使能源效率提高10.6倍。重新设计加速器以适应超导技术的独特限制（例如低扇出），将能量效率提高到12.2倍。我们还研究了使加速器能够容忍新故障模式的解决方案，并展示了如何利用这种容错设计来降低工作电流，从而将整体能效提高到CMOS的46倍。我们的论文还开发了一个工作流程，用于评估超导技术内置的加速器的面积，性能和功率，该工作流程可以帮助其他研究人员探索使用该技术的设计。
英文摘要：
As the scaling of conventional CMOS-based technologies slows down, there is growing interest in alternative technologies that can improve performance or energy-efficiency. Superconducting circuits based on Josephson Junction (JJ) is an emerging technology that can provide devices which can be switched with pico-second latencies and consuming two orders of magnitude lower switching energy compared to CMOS. While JJ-based circuits can provide high operating frequency and energy-efficiency, this technology faces three critical challenges: limited device density and lack of area-efficient technology for memory structures, reduced gate fanout compared to CMOS, and new failure modes of Flux-Traps that occurs due to the operating environment. The lack of dense memory technology restricts the use of superconducting technology in the near term to application domains that have high compute intensity but require negligible amount of memory. In this paper, we study the use of superconducting technology to build an accelerator for SHA-256 engines commonly used in Bitcoin mining applications. We show that merely porting existing CMOS-based accelerator to superconducting technology provides 10.6X improvement in energy efficiency. Redesigning the accelerator to suit the unique constraints of superconducting technology (such as low fanout) improves the energy efficiency to 12.2X. We also investigate solutions to make the accelerator tolerant of new fault modes and show how this fault-tolerant design can be leveraged to reduce the operating current, thereby increasing the overall energy-efficiency to 46X compared to CMOS. Our paper also develops a workflow for evaluating area, performance, and power for accelerators built in superconducting technology, and this workflow can help other researchers explore designs using this technology.
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