本文提出了一种新型的高性能、高可靠性的5 T CMOS SRAM设计，并与传统的低功耗6 T SRAM进行了比较，说明了该设计如何降低动态功耗。该设计可用作处理器和低功耗便携式设备中的高速缓冲存储器。与传统的6 T单元相比，所提出的SRAM单元具有约13%的面积减少，并且具有独特的位线和负电源电压偏置方法和接地控制架构，以提高性能，并抑制待机泄漏功率。
英文摘要：
This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and low-power portable devices. The proposed SRAM cell features ~13% area reduction compared to a conventional 6T cell, and features a unique bit-line and negative supply voltage biasing methodology and ground control architecture to enhance performance, and suppress standby leakage power.
This paper presents an in-memory computing (IMC) architecture for image denoising. The proposed SRAM based in-memory processing framework works in tandem with approximate computing on a binary image generated from neuromorphic vision sensors. Implemented in TSMC 65nm process, the proposed architecture enables approximately 2000X energy savings (approximately 222X from IMC) compared to a digital implementation when tested with the video recordings from a DAVIS sensor and achieves a peak throughput of 1.25-1.66 frames/us.
State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is based on the analog behavior of the data stored inside the memory cell. These approaches proposed various system architectures for that. In this paper, we investigated the effect of threshold voltage suppression on the access transistors of the In-SRAM multiplication and accumulation (MAC) accelerator to improve and enhance the performance of bit line (bit …
In this paper, we present a new 9T SRAM cell that has good write-ability and improves read stability at the same time. Simulation results show that the proposed design increases Read SNM (RSNM) and Ion/Ioff of read path by 219% and 113%, respectively at supply voltage of 300mV over conventional 6T SRAM cell in a 90nm CMOS technology. Proposed design lets us to reduce minimum operating voltage of SRAM (VDDmin) to 350mV, whereas conventional 6T SRAM cannot operate successfully with acceptable failure rate at supply voltages bellow 725mV. We also compared our design with three other SRAM cells fr…
In this paper, we propose a novel memory-centric scheme based on CMOS SRAM for acceleration of data intensive applications. Our proposal aims at dynamically increasing the on-chip memory storage capacity of SRAM arrays on-demand. The proposed scheme called - Augmented Memory Computing allows an SRAM cell to operate in two different modes 1) the Normal mode and 2) the Augmented mode. In the Normal mode of operation, the SRAM cell functions like a standard 6 transistor (6T) SRAM cell, storing one bit of data in static format. While in the Augmented mode, each SRAM cell can store >1 bit of data (…
This paper presents a low cost PMOS-based 8T (P-8T) SRAM Compute-In-Memory (CIM) architecture that efficiently per-forms the multiply-accumulate (MAC) operations between 4-bit input activations and 8-bit weights. First, bit-line (BL) charge-sharing technique is employed to design the low-cost and reliable digital-to-analog conversion of 4-bit input activations in the pro-posed SRAM CIM, where the charge domain analog computing provides variation tolerant and linear MAC outputs. The 16 local arrays are also effectively exploited to implement the analog mul-tiplication unit (AMU) that simultaneo…
ETH Zürich（苏黎世联邦理工学院）；University of Bologna（博洛尼亚大学）
Binary Neural Networks (BNNs) have been shown to be robust to random bit-level noise, making aggressive voltage scaling attractive as a power-saving technique for both logic and SRAMs. In this work, we introduce the first fully programmable IoT end-node system-on-chip (SoC) capable of executing software-defined, hardware-accelerated BNNs at ultra-low voltage. Our SoC exploits a hybrid memory scheme where error-vulnerable SRAMs are complemented by reliable standard-cell memories to safely store critical data under aggressive voltage scaling. On a prototype in 22nm FDX technology, we demonstrate…
DeltaKWS: A 65nm 36nJ/Decision Bio-inspired Temporal-Sparsity-Aware Digital Keyword Spotting IC with 0.6V Near-Threshold SRAM
Institute of Neuroinformatics, University of Zürich and ETH Zürich（苏黎世大学与苏黎世联邦理工学院神经信息学研究所）；Leiden Institute of Advanced Computer Science (LIACS), Leiden University（莱顿大学高级计算机科学研究所）；Department of Electronics and Nanoengineering, School of Electrical Engineering, Aalto University（阿尔托大学工程学院电子与纳米工程系）；Department of Microelectronics, Delft University of Technology（代尔夫特理工大学微电子系）
Accelerating finite automata processing is critical for advancing real-time analytic in pattern matching, data mining, bioinformatics, intrusion detection, and machine learning. Recent in-memory automata accelerators leveraging SRAMs and DRAMs have shown exciting improvements over conventional digital designs. However, the bit-vector representation of state transitions used by all SOTA designs is only optimal in processing worst-case completely random patterns, while a significant amount of memory and energy is wasted in running most real-world benchmarks. We present CAMA, a Content-Addressabl…
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Department Computer Science \& Technology, BNRist, Tsinghua University, Beijing, China + Department of Computer Science \& Engineering, The Chinese University of Hong Kong, Hong Kong SAR；Department Computer Science \& Technology, BNRist, Tsinghua University, Beijing, China；+ Department of Computer Science \& Engineering, The Chinese University of Hong Kong, Hong Kong SAR
Public key cryptography protocols, such as RSA and elliptic curve cryptography, will be rendered insecure by Shor's algorithm when large-scale quantum computers are built. Cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate. However, high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on low-power embedded devices. To address this challenge, we present Sapphire - a lattice cryptography processor with configurable parameters. Efficient sampling, with a SHA-3-based PRNG…
Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for low-power applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly…
