面向低功耗脉冲神经网络的非均匀内存分区
Non-uniform Memory Partitioning For Low-Power Spiking Neural Networks
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中文总结 AI 辅助
该研究针对脉冲神经网络突触权重内存功耗过高的问题,提出非均匀内存分区架构,经28nm CMOS工艺验证,可实现最高61%的功耗降低且面积开销仅为传统均匀分区的约47.6%。
中文摘要 AI 辅助
脉冲神经网络(SNN)在处理时序丰富且稀疏的数据方面天然具有优势,但由于其采用时间步长处理方式,内存访问(尤其是对存储在静态随机存取存储器(SRAM)中的突触权重的访问)往往是总功耗的主要来源。为解决该问题且不产生大面积开销,我们提出利用网络中神经元的平均发放率存在的巨大差异,将突触权重高效分配到由多个非均匀大小的内存体组成的片上内存中。通过将频繁发放神经元的权重分配到浅层、低访问成本的内存,将访问频率较低的权重分配到更深层、高密度的内存,可在不产生大面积开销的情况下降低突触权重内存的平均功耗。为对我们提出的架构进行基准测试并找到内存配置的最优方案,我们基于应用需求和硬件约束执行自动探索。对于采用28纳米CMOS工艺综合的内存设计,我们的架构相比传统设计可实现高达61%的突触权重内存访问功耗降低,且与实现相当降低效果的传统均匀分区内存体相比,面积开销降低了2.1倍。
英文摘要
Spiking Neural Networks (SNNs) naturally excel in processing temporally rich and sparse data. However, because of their time-stepped processing, memory access, specifically to synaptic weights stored in SRAM (static random-access memory), tends to dominate total power consumption. To address this issue, without incurring a large area overhead, we propose to leverage the greatly varying average firing rate of neurons in the network to efficiently allocate synaptic weights to an on-chip memory consisting of multiple non-uniformly sized memory banks. By assigning weights of frequently firing neurons to shallow, low-access cost memory and less actively accessed weights to deeper, high-density memories, the average power consumption of the synaptic weight memory is decreased without incurring a large area overhead. To benchmark our proposed architecture and find optimal configurations of memory arrangements, we perform an automatic exploration based on application requirements and hardware constraints. For memory designs synthesized in 28-nm CMOS technology, we show that our architecture can achieve a synaptic weight memory access power reduction of up to 61\% compared to a conventional design, with a 2.1$\times$ lower area overhead, as compared to a traditional uniformly partitioned memory bank that achieves a comparable reduction.
发表机构
- Department of Electrical and Computer Engineering, Aarhus University, Denmark(奥胡斯大学电气与计算机工程系)
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