AI 中文总结
针对嵌入式RISC-V处理器指令获取能耗大的问题，提出动态和静态循环缓存架构，经在NEORV32处理器及特定工作负载上评估，动态缓存减48.3%指令获取与21.5%总能量，静态缓存更优，且面积开销低，完整实现开源。
AI 中文摘要
嵌入式RISC-V处理器越来越多地用于边缘设备上的人工智能推理，其中能源效率是主要设计约束。基于SRAM的内存中的指令获取是这些内核中主要的能量消耗源，在我们的基线测量中占总能量的40%以上。本文提出了两种集成到RISC-V处理器数据路径中的循环缓存架构：一种动态循环缓存，在运行时自动检测并缓存短的向后分支循环；一种静态循环缓存，用作软件管理的热代码指令缓冲区，允许在引导序列期间预加载任意指令块。两种设计都在开源的NEORV32 RISC-V处理器中实现，并在LeNet-5卷积神经网络推理工作负载上进行评估，该工作负载在GlobalFoundries 22nm FDX+技术上以0.5V和250MHz进行合成。动态缓存减少了48.3%的指令获取和21.5%的总能量，而静态缓存实现了83.3%的获取减少和35.5%的总能量节省。两种设计的面积开销均低于整个SoC面积的0.2%。完整实现是开源的。
英文摘要
Embedded RISC-V processors are increasingly deployed for on-device AI inference at the edge, where energy efficiency is a primary design constraint. Instruction fetching from SRAM-based memory is a dominant source of energy consumption in these cores, accounting for over 40\% of total energy in our baseline measurements. This paper presents two loop cache architectures integrated into the datapath of a RISC-V processor: a dynamic loop cache that automatically detects and caches short backward-branch loops at runtime, and a static loop cache that functions as a software-managed hot-code instruction buffer, allowing preloading of arbitrary instruction blocks during the boot sequence. Both designs are implemented in the open-source NEORV32 RISC-V processor and evaluated on a LeNet-5 convolutional neural network inference workload, synthesized on GlobalFoundries 22nm FDX+ technology at 0.5\,V and 250\,MHz. The dynamic cache reduces instruction fetches by 48.3\% and total energy by 21.5\%, while the static cache achieves an 83.3\% fetch reduction and 35.5\% total energy savings. The area overhead of both designs remains below 0.2\% of the full SoC area. The complete implementation is open source.
CommentsAccepted for publication in the IEEE MCSoC 2026 Conference
