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arXiv 2602.01422physics.ins-det
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PCIe400通用读出板资格测试

PCIe400 generic readout board qualification test

European Organization for Nuclear Research (CERN)(欧洲核子研究组织(CERN))
Kevin Arnaud, Antoine Back, Daniel Charlet, Gabriel Degret, Luigi Del Buono, Paolo Durante, Amaury Hervo, Frédéric Hachon, Xavier Lafay, Julien Langouët, Renaud… 展开作者

Kevin Arnaud, Antoine Back, Daniel Charlet, Gabriel Degret, Luigi Del Buono, Paolo Durante, Amaury Hervo, Frédéric Hachon, Xavier Lafay, Julien Langouët, Renaud Le Gac, Jea-Luc Meunier, Jean-Marc Nappa, Costy Nassif Mattar, Christophe Renard, Guillaume Vouters

AI总结:

本文针对PCIe400通用读出板的高带宽接口和确定性时钟分布进行资格测试,以满足未来高能物理实验对200Tbps吞吐量的需求。

摘要:

PCIe400是一种为未来高能物理实验高吞吐量数据采集设计的通用读出板。它支持最多48个双向链路,提供1至26 Gbps的定制协议,以达到最高400 Gbps的带宽。该板作为LHCb升级II的技术演示平台,预计总吞吐量约为200 Tbps。此外,PCIe400还针对前端电子设备的确定性时钟分布进行设计。在最大瞬时亮度为$1.5~\times~10^{34}~cm^{-2}s^{-1}$的情况下,LHCb升级II预计每束流中有高达40个质子-质子相互作用。采用时间分辨率低于20 ps的4D跟踪探测器,促使需要在超过2000个节点的大型系统中实现峰值对峰值低于10 ps的确定性时钟分布。本文介绍了PCIe400原型板的资格测试,重点在于高带宽接口,包括下一代QSFP112链路和确定性时钟分布。

英文摘要:

The PCIe400 is a generic readout board designed for high-throughput data acquisition in future high-energy physics experiments. It interfaces up to 48 bidirectional links supporting custom protocols from 1 to 26 Gbps to modern back-end systems providing up to 400 Gbps bandwidth.The board is developed as a technological demonstrator for the LHCb Upgrade II, which foresees an aggregated throughput of approximately 200 Tbps. In addition to increased bandwidth, the PCIe400 targets deterministic clock distribution to front-end electronics. At a maximum instantaneous luminosity of $1.5~\times~10^{34}~cm^{-2}s^{-1}$, up to 40 proton-proton interactions per bunch crossing are expected in LHCb Upgrade II. The adoption of 4D tracking detectors with time resolutions down to 20 ps motivates clock distribution with phase determinism below 10 ps peak-to-peak across large-scale systems exceeding 2000 nodes. This paper presents the qualification of the PCIe400 prototype board, focusing on high-bandwidth interfaces, including next-generation QSFP112 links, and phase-deterministic clock distribution.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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