Intel Stratix 10 FPGA设计用于HL-LHC中ATLAS实验的径迹重建
Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC
AI总结：
本文介绍了用于ATLAS实验硬件径迹触发系统的PRM板FPGA设计，该设计利用联想存储器和线性化算法实现径迹重建，并在仿真和硬件测试中验证了功能。
摘要：
高效率且高质量的带电粒子径迹快速重建是高亮度LHC中ATLAS实验在线数据选择的关键部分。为评估硬件径迹触发（HTT）系统的可行性，已开发了专用的定制硬件板和软件仿真。作为HTT系统的一部分，模式识别夹层板（PRM）被设计用于利用联想存储器ASIC识别硅探测器中的候选径迹，并使用在Intel Stratix 10 MX FPGA中实现的线性化算法来选择和重建径迹。这种高度并行化的FPGA设计大量使用了集成的High-Bandwidth-Memory。本文介绍了PRM板的FPGA设计。其功能已在仿真和基于Intel Stratix 10 MX开发套件的硬件测试中得到了验证。
英文摘要：
The fast reconstruction of charged particle tracks with high efficiency and track quality is an essential part of the online data selection for the ATLAS experiment at the High-Luminosity LHC. Dedicated custom designed hardware boards and software simulations have been developed to assess the feasibility of a Hardware Tracking Trigger (HTT) system. The Pattern Recognition Mezzanine (PRM), as part of the HTT system, has been designed to recognize track candidates in silicon detectors with Associative Memory ASICs and to select and reconstruct tracks using linearized algorithms implemented in an Intel Stratix 10 MX FPGA. The highly parallelized FPGA design makes extensive use of the integrated High-Bandwidth-Memory. In this paper, the FPGA design for the PRM board is presented. Its functionalities have been verified in both simulations and hardware tests on an Intel Stratix 10 MX development kit.
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