arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2011.11316cond-mat.mes-hallphysics.app-ph
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2-说明Input 4-Output Logic Gate

2-input 4-output Programmable Spin Wave Logic Gate

Abdulqader Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana

摘要:

为了将基于自旋波(SW)的计算范例付诸实践并开发超低功率Magnonic电路和计算平台,需要基本逻辑门,其在SW域内操作并可以级联,而不需要SW域和电压域之间的来回转换。为了实现这一点,SW门必须具有内在的扇出能力,输入输出数据表示一致,和可重构。在本文中,我们解决的第一个和最后一个要求,并提出了一种新的4输出可编程SW逻辑。首先,我们介绍了门的结构,并证明,通过调整门的输出检测方法,它可以并行计算任何4元素的子集的2输入布尔函数集与,与非,或,或非,异或,和XNOR。此外,我们调整结构,使其所有4个输出产生具有相同能量的SW,并证明它可以评估布尔函数集,同时提供从1到4的扇出能力。我们通过实例化和模拟不同的门配置,如4-输出AND/OR,4-输出XOR/XNOR,输出能量平衡的4-输出AND/OR,和输出能量平衡的4-输出XOR/XNOR,通过面向对象的微磁框架(OOMMF)模拟验证我们的方法。最后,我们评估我们的建议在延迟和能耗方面的性能,并将其与现有的最先进的SW和16纳米CMOS同行进行比较。结果表明,对于相同的功能,我们的方法提供了3倍和16倍的能量减少,与传统的SW和16纳米CMOS实现相比,分别。

英文摘要:

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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