In this paper, we develop a new classical simulation of quantum bit (qubit) by use of analog components in order to be able to simulate the quantum properties such as the superposition of states. As part of this new approach, we have also implemented many logical gates (Pauli-X, Hadamard, and Conditional phase-shift gates). Simulation of Hadamard and Conditional phase-shift gates using Proteus Design Suite is also presented and discussed in this work.
We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fedback or fedforward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state ass…
We introduce a data bus, for reducing the qubit counts within quantum computations (protected by surface codes). For general computations, an automated trade-off analysis (software tool and source code are open sourced and available online) is performed to determine to what degree qubit counts are reduced by the data bus: is the time penalty worth the qubit count reductions? We provide two examples where the qubit counts are convincingly reduced: 1) interaction of two surface code patches on NISQ machines with 28 and 68 qubits, and 2) very large-scale circuits with a structure similar to state…
As a variety of quantum computing models and platforms become available, methods for assessing and comparing the performance of these devices are of increasing interest and importance. Despite being built of the same fundamental computational unit, radically different approaches have emerged for characterizing the performance of qubits in gate-based and quantum annealing computers, limiting and complicating consistent cross-platform comparisons. To fill this gap, this work proposes a single-qubit protocol (Q-RBPN) for measuring some basic performance characteristics of individual qubits in bot…
The hardware overhead associated with microwave control is a major obstacle to scale-up of superconducting quantum computing. An alternative approach involves irradiation of the qubits with trains of Single Flux Quantum (SFQ) pulses, pulses of voltage whose time integral is precisely equal to the superconducting flux quantum. Here we describe the derivation and validation of compact SFQ pulse sequences in which classical bits are clocked to the qubit at a frequency that is roughly a factor 5 higher than the qubit oscillation frequency, allowing for variable pulse-to-pulse timing. The control s…
QuBE/Qubex: an integrated hardware-software system for superconducting qubit experiments with broadband control
Graduate School of Engineering Science, The University of Osaka（大阪大学大学院工程学研究科）；Center for Quantum Information and Quantum Biology, The University of Osaka（大阪大学量子信息与量子生物学中心）；QuEL, Inc.（QuEL公司）；e-trees.Japan, Inc.（e-trees.Japan公司）
In this work we extend a multi-qubit benchmarking technique known as the Binned Output Generation (BOG) in order to discriminate between coherent and incoherent noise sources in the multi-qubit regime. While methods exist to discriminate coherent from incoherent noise at the single and few-qubit level, these methods scale poorly beyond a few qubits or must make assumptions about the form of the noise. On the other end of the spectrum, system-level benchmarking techniques exist, but fail to discriminate between coherent and incoherent noise sources. We experimentally verify the BOG against Rand…
We introduce a volumetric benchmark for near-term quantum platforms based on the generation and verification of genuine entanglement across n-qubits using graph states and direct stabilizer measurements. Our benchmark evaluates the robustness of multipartite and bipartite n-qubit entanglement with respect to many sources of hardware noise: qubit decoherence, CNOT and swap gate noise, and readout error. We demonstrate our benchmark on multiple superconducting qubit platforms available from IBM (ibmq_belem, ibmq_toronto, ibmq_guadalupe and ibmq_jakarta). Subsets of $n<10$ qubits are used for gra…
Leakage outside of the qubit computational subspace poses a threatening challenge to quantum error correction (QEC). We propose a scheme using two leakage-reduction units (LRUs) that mitigate these issues for a transmon-based surface code, without requiring an overhead in terms of hardware or QEC-cycle time as in previous proposals. For data qubits we consider a microwave drive to transfer leakage to the readout resonator, where it quickly decays, ensuring that this negligibly affects the coherence within the computational subspace for realistic system parameters. For ancilla qubits we apply a…
Performing efficient quantum computer tuneup and calibration is essential for growth in system complexity. In this work we explore the link between facilitating such capabilities and the underlying architecture of the physical hardware. We focus on the specific challenge of measuring (``mapping'') spatially inhomogeneous quasi-static calibration errors using spectator qubits dedicated to the task of sensing and calibration. We introduce a novel architectural concept for such spectator qubits: arranging them spatially according to prescriptions from optimal 2D approximation theory. We show that…
From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware
School of Computing and Information Systems, Singapore Management University（新加坡管理大学计算与信息系）；Institute of High Performance Computing, A*STAR（A*STAR高性能计算研究所）
Quantum computers may provide good solutions to combinatorial optimization problems by leveraging the Quantum Approximate Optimization Algorithm (QAOA). The QAOA is often presented as an algorithm for noisy hardware. However, hardware constraints limit its applicability to problem instances that closely match the connectivity of the qubits. Furthermore, the QAOA must outpace classical solvers. Here, we investigate swap strategies to map dense problems into linear, grid and heavy-hex coupling maps. A line-based swap strategy works best for linear and two-dimensional grid coupling maps. Heavy-he…
We propose a new method to autonomously correct for errors of a logical qubit induced by energy relaxation. This scheme encodes the logical qubit as a multi-component superposition of coherent states in a harmonic oscillator, more specifically a cavity mode. The sequences of encoding, decoding and correction operations employ the non-linearity provided by a single physical qubit coupled to the cavity. We layout in detail how to implement these operations in a practical system. This proposal directly addresses the task of building a hardware-efficient and technically realizable quantum memory.
Generating high-fidelity, tunable entanglement between qubits is crucial for realizing gate-based quantum computation. In superconducting circuits, tunable interactions are often implemented using flux-tunable qubits or coupling elements, adding control complexity and noise sources. Here, we realize a tunable $ZZ$ interaction between two transmon qubits with fixed frequencies and fixed coupling, induced by driving both transmons off-resonantly. We show tunable coupling over one order of magnitude larger than the static coupling, and change the sign of the interaction, enabling cancellation of …
The utility of classical neural networks as universal approximators suggests that their quantum analogues could play an important role in quantum generalizations of machine-learning methods. Inspired by the proposal in [Torrontegui and García-Ripoll 2019 EPL 125 30004], we demonstrate a superconducting qubit implementation of an adiabatic controlled gate, which generalizes the action of a classical perceptron as the basic building block of a quantum neural network. We show full control over the steepness of the perceptron activation function, the input weight and the bias by tuning the adiabat…
Designing and implementing algorithms for medium and large scale quantum computers is not easy. In previous work we have suggested, and developed, the idea of using machine learning techniques to train a quantum system such that the desired process is "learned," thus obviating the algorithm design difficulty. This works quite well for small systems. But the goal is macroscopic physical computation. Here, we implement our learned pairwise entanglement witness on Microsoft's Q#, one of the commercially available gate model quantum computer simulators; we perform statistical analysis to determine…
Hardware-Aware Fermion-to-Qubit Mappings for Simulating the 2D Hubbard Model on Heavy-Hexagon Quantum Processors
University of Milano-Bicocca（米兰比可卡大学）；INFN Milano-Bicocca（意大利国家核物理研究所米兰比可卡分部）；Bicocca Quantum Technologies (BiQuTe) Centre（比可卡量子技术中心）；University of Helsinki（赫尔辛基大学）；HUN-REN Wigner Research Centre for Physics（匈牙利研究与教育网络维格纳物理研究中心）；Algorithmiq Ltd（算法有限公司）；University of Florence（佛罗伦萨大学）；INFN Firenze（意大利国家核物理研究所佛罗伦萨分部）
Quantum computing has great potential for advancing machine learning algorithms beyond classical reach. Even though full-fledged universal quantum computers do not exist yet, its expected benefits for machine learning can already be shown using simulators and already available quantum hardware. In this work, we focus on distance-based classification using actual early stage quantum hardware. We extend earlier work and present a distance-based classification algorithm using only two qubits. We show that the results are similar to the theoretically expected results.
In May 2016 IBM released access to its 5-qubit quantum computer to the scientific community, its "IBM Quantum Experience" since acquiring over 25,000 users from students, educators and researchers around the globe. In the short time since the "IBM Quantum Experience" became available, a flurry of research results on 5-qubit systems have been published derived from the platform hardware. Quintuple is an open-source object-oriented Python module implementing the simulation of the "IBM Quantum Experience" hardware. Quintuple quantum algorithms can be programmed and run via a custom language fully…
Due to several physical limitations in the realisation of quantum hardware, today's quantum computers are qualified as Noisy Intermediate-Scale Quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realisations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbour connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual…
In this work we experimentally demonstrate how generative model training can be used as a benchmark for small ($<5$ qubits) quantum devices. Performance is quantified using three data analytic metrics: the Kullbeck-Leiber divergence, and two adaptations of the F1 score. Using the $2\times2$ Bars and Stripes dataset, we determine optimal circuit constructions for generative model training on superconducting qubits by including hardware connectivity constraints into circuit design. We show that on noisy hardware sparsely connected, shallow circuits out-perform denser counterparts.
Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed b…
Universal quantum computers require a large network of qubits robust against errors. Recent theoretical and experimental studies on donor nuclear spins in silicon, engineered on semiconductor platforms compatible with industrial fabrication, show their coherent behavior and potential for scalability. Here we present a hardware-efficient quantum protocol that corrects phase flips of a nuclear spin using explicit experimentally feasible operations. We introduce the MAUS encoding (Moment AngUlar System encoding) which uses the large Hilbert space provided by the nuclear spin of the donor to encod…
Hybrid quantum systems in which acoustic resonators couple to superconducting qubits are promising quantum information platforms. High quality factors and small mode volumes make acoustic modes ideal quantum memories, while the qubit-phonon coupling enables the initialization and manipulation of quantum states. We present a scheme for quantum computing with multimode quantum acoustic systems, and based on this scheme, propose a hardware-efficient implementation of a quantum random access memory (QRAM). Quantum information is stored in high-Q phonon modes, and couplings between modes are engine…
Hardware-Tailored Resource Estimation for Magic-State Distillation on Silicon Spin Qubits
Cavendish Lab., Department of Physics, Univ. of Cambridge（剑桥大学卡文迪什实验室物理系）；Hitachi Cambridge Lab.（日立剑桥实验室）；Department of Computer Science and Technology, Univ. of Cambridge（剑桥大学计算机科学与技术系）
The prospect of computational hardware with quantum advantage relies critically on the quality of quantum gate operations. Imperfect two-qubit gates is a major bottleneck for achieving scalable quantum information processors. Here, we propose a generalizable and extensible scheme for a two-qubit coupler switch that controls the qubit-qubit coupling by modulating the coupler frequency. Two-qubit gate operations can be implemented by operating the coupler in the dispersive regime, which is non-invasive to the qubit states. We investigate the performance of the scheme by simulating a universal tw…
Shallow instantaneous quantum polynomial-time circuits for generative modeling on noisy intermediate-scale quantum hardware
Eurecat, Centre Tecnològic de Catalunya（Eurecat，加泰罗尼亚技术中心）；Centre de Visió per Computador (CVC)（计算机视觉中心）；Universitat Autònoma de Barcelona (UAB)（巴塞罗那自治大学）
Characterizing and mitigating errors in current noisy intermediate-scale devices is important to improve performance of next generations of quantum hardware. In order to investigate the importance of the different noise mechanisms affecting quantum computation, we perform full quantum process tomography of single qubits in a real quantum processor in which echo experiments are implemented. Besides error sources already included in standard models, the obtained results show the dominant role of coherent errors, which we practically correct by inserting random single-qubit unitaries in the quant…
The optimal design of a fault-tolerant quantum computer involves finding an appropriate balance between the burden of large-scale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution of quantum logic operations on a realistic quantum hardware containing limited computational resources. In this work, we report a complete performance simulation software tool capable of (1) searching the hardware design space by varying resource architecture and technology parameters, (2) synthesizi…
As the nascent field of quantum computing develops, an increasing number of quantum hardware modalities, such as superconducting electronic circuits, semiconducting spins, trapped ions, and neutral atoms, have become available for performing quantum computations. These quantum hardware modalities exhibit varying characteristics and implement different universal quantum gate sets that may e.g. contain several distinct two-qubit quantum gates. Adapting a quantum circuit from a, possibly hardware-agnostic, universal quantum gate set to the quantum gate set of a target hardware modality has a cruc…
Protein folding on a 64 qubit trapped-ion hardware via counterdiabatic quantum optimization
Kipu Quantum GmbH（Kipu Quantum有限公司）；University of the Basque Country EHU（巴斯克大学）；Instituto de Ciencia de Materiales de Madrid (ICMM-CSIC)（马德里材料科学研究所）；Universidad Autónoma de Madrid（马德里自治大学）；University of Valencia（瓦伦西亚大学）；IonQ Inc.（IonQ公司）
As the variety of commercially available quantum computers continues to increase so does the need for tools that can characterize, verify and validate these computers. This work explores using quantum state tomography for characterizing the performance of individual qubits and develops a vector field visualization for presentation of the results. The proposed protocol is demonstrated in simulation and on quantum computing hardware developed by IBM. The results identify qubit performance features that are not reflected in the standard models of this hardware, indicating opportunities to improve…
We focus on the depth optimization of CNOT circuits on hardwares with limited connectivity. We adapt the algorithm from Kutin et al. that implements any $n$-qubit CNOT circuit in depth at most $5n$ on a Linear Nearest Neighbour (LNN) architecture. Our proposal is a block version of Kutin et al.'s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have the less the depth. We derive better theoretical upper bounds and we provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on so…
