$β$-Ga$_{2}$O$_{3}$ based enhancement mode transistor designs are critical for the realization of low loss, high efficiency next generation power devices with rudimentary driving circuits. A novel approach towards attaining a high positive flat band voltage (V$_{fb}$) of 10.6 V in $β$-Ga$_{2}$O$_{3}$ metal-oxide-semiconductor capacitors (MOSCAPs), with the ability to fine tune it between 3.5 V to 10.6 V, using a polycrystalline AlN charge trap layer has been demonstrated. This can enable enhancement mode operation over a wide doping range. Excellent V$_{fb}$ retention of ${\sim}$97% for 10$^{4}$ s at 55 $^{\circ}$C was exhibited by the gate stacks after charge trapping, hence reducing the requirement of frequent charge injection cycles. In addition, low gate leakage current density (J$_{g}$) for high negative gate voltages (V$_{g}$${\sim}$-60 V) indicates the potential of this gate stack to enable superior breakdown characteristics in enhancement mode transistors.
The decoupling of epitaxial factors influencing on the dynamic instabilities of AlGaN/GaN metal-insulator semiconductor high electron mobility transistors is investigated. Three different sets of samples have been analyzed by means of dynamic instabilities in the threshold voltage (V$_{\mathrm{th}}$ shift). Secondary ion mass spectroscopy, steady-state photoluminescence (PL) measurements have been performed in conjunction with electrical characterization. The device dynamic performance is found to be significantly dependent on both the C concentration close to the channel as well as on the dis…
We report on electronic transport in dual-gate, artificially stacked bilayer graphene field effect transistors (BiGFETs) fabricated from large-area chemical vapor deposited (CVD) graphene. The devices show enhanced tendency to current saturation, which leads to reduced minimum output conductance values. This results in improved intrinsic voltage gain of the devices when compared to monolayer graphene FETs. We employ a physics based compact model originally developed for Bernal stacked bilayer graphene FETs (BSBGFETs) to explore the observed phenomenon. The improvement in current saturation may…
The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-free experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High…
We have decomposed the modeling of the field-effect transistors into the two independent parts: the current continuity based kinetics and the charge neutrality based electrostatics. The former part, that is universal for all FETs, leads to an explicit and closed form of I-V characteristics as a function of the total channel charge. The latter part, which is specific for a particular material and geometric configurations can be considered as an independent engineering task. The quantum capacitance and the interface trap density are consistently incorporated into the solution of the current cont…
A novel design-friendly device called the transistor-injected dual doping quantum cascade laser (TI-D2QCL) with two different doping in each stack of a homogeneous superlattice is proposed. By adjusting the base-emitter bias Vbe of the bipolar transistor to supply electrons in the dual doping regions, charge quasi-neutrality can be achieved to generate different optical transitions in each cascading superlattice stack. These transitions are then stacked and amplified to contribute to a broad flat gain spectrum. Model calculations of a designed TI- D2QCL show that a broad flat gain spectrum ran…
In this work it is reported a vertical electrolyte transistor (VET) whose structure is based on stacked layers as described below: bottom contact (source or drain) - channel - permeable intermediate electrode (drain or source) - ion gel (electrolyte gate dielectric) - gate top contact. This VET depicts versatility to work as Electrolyte-Gated Vertical Organic Field Effect Transistor (Electrolyte-Gated VOFET) or Vertical Organic Electrochemical Transistor (VOECT) as never reported before. The distinction of these operation modes is regarding to the transistor transconductance that occurs due to…
Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics
Gwangju Institute of Science and Technology（光州科学技术院）；Ulsan National Institute of Science and Technology（蔚山科学技术院）；Aalto University（阿尔托大学）；VTT Technical Research Centre of Finland Ltd.（芬兰技术研究中心有限公司）；Sungkyunkwan University（成均馆大学）；Korea Research Institute of Chemical Technology（韩国化学技术研究所）；OtaNano-Nanomicroscopy Center, Aalto University（阿尔托大学奥塔纳米显微镜中心）；Yonsei University（延世大学）；Beijing Institute of Technology（北京理工大学）；Nanyang Technological University（南洋理工大学）；Arizona State University（亚利桑那州立大学）；Seoul National University（首尔国立大学）；University of Cambridge（剑桥大学）
Lead-halide perovskites emerged as novel semiconducting materials suitable for a variety of optoelectronic applications. However, fabrication of reliable perovskite field-effect transistors (FETs), the devices necessary for the fundamental and applied research on charge transport properties of this class of materials, has proven challenging. Here we demonstrate high-performance perovskite FETs based on epitaxial, single crystalline thin films of cesium lead bromide (CsPbBr3). An improved vapor-phase epitaxy has allowed growing truly large-area, atomically flat films of this perovskite with exc…
Inspired by experimental observations related to electrolyte-gated transistors (EGTs) where non-ideals behaviors are shown and not described by just one theoretical model, we proposed a charge carriers transport model able to describe the typical modes of operation profiles as well as some non-ideals ones from electrolyte-gated field effect transistors (EGOFETs) and organic electrochemical transistors (OECTs). Our analysis include the effect of 2D or 3D percolation transport (PT) and also the influence of a shallow exponential traps distribution on the transport. Under these considerations, a …
In this paper, we investigated the performance of thin-film transistors (TFTs) with different channel configurations including single-active-layer (SAL) Sn-Zn-O (TZO), dual-active-layers (DAL) In-Sn-O (ITO)/TZO, and triple-active-layers (TAL) TZO/ITO/TZO. The TAL TFTs were found to combine the advantages of SAL TFTs (a low off-state current) and DAL TFTs (a high mobility and a low threshold voltage). The proposed TAL TFTs exhibit superior electrical performance, e.g. a high on-off state current ratio of 2*10^8, a low threshold voltage of 0.52 V, a high saturation mobility of 145.2 cm2/Vs, and …
Organic water-gated thin-film transistors (WG-TFTs) are of great interest in developing low-cost and high-performance biosensors. The device's sensitivity to changes in measurement conditions can impair long-term operation, and care must be taken to ensure that the WG-TFT sensor response is due to an actual biorecognition event occurring on the sensing electrode. This work aims to clarify the long-term stability of a poly-3-hexylthiophene (P3HT) WG-TFT operated intermittently over two months during 5750 measurement cycles. We have evaluated the device figures of merit (FOM), such as threshold …
The development of thin film transistor (TFTs) based integrated circuits on flexible substrates promise interesting approaches to human interface systems. Recently TFTs have been fabricated on textured surfaces such as textiles, paper, artificially corrugated or dimpled substrates, threads and fibers. This can result in the TFTs metal-insulator-semiconductor (MIS) stack being significantly distorted from a planar zero-curvature geometry to having non zero and potentially high curvature. Although the direct deposition on textured surfaces do not result in mechanical stress (as for example in be…
Field-effect transistors (FETs) with non-covalently functionalised molybdenum disulfide (MoS2) channels grown by chemical vapour deposition (CVD) on SiO2 are reported. The dangling-bond-free surface of MoS2 was functionalised with a perylene bisimide derivative to allow for the deposition of Al2O3 dielectric. This allowed the fabrication of top-gated, fully-encapsulated MoS2 FETs. Furthermore, by the definition of vertical contacts on MoS2, devices, in which the channel area was never exposed to polymers, were fabricated. The MoS2 FETs showed high mobilities for transistors fabricated on SiO2 …
Recent measurements on ultra-thin body Negative Capacitance Field Effect Transistors have shown subthreshold behaviors that are not expected in a classical MOSFET. Specifically, subthreshold swing was found to decrease with increased gate bias in the subthreshold region for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the subthreshold swing relative to control devices showed a non-monotonic dependence on the gate length. In this paper, using a Landau-Khanatnikov ferroelectric gate stack model calibrated with measured Capacitance-Voltage, we show that b…
In this report, the hysteresis behaviors of PEI:LiClO4 and PEG:LiClO4 electrolyte gate and back gate Graphene-on-SiO2 FET were analyzed by gate-voltage source-drain current modulation. It is shown that both the sweeping rate and the sweep range will cause hysteresis behaviors in the form of Dirac Point shifting or changes in the current. Different mechanisms including charge trapping and electrical double layer capacitive effect are proposed to explain the behavior qualitatively on both back gated and electrolyte gated FET and partially confirmed with the present experimental results.
The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultr…
In this work, we demonstrate enhancement-mode field-effect transistors by atomic-layer-deposited (ALD) amorphous In2O3 channel with thickness down to 0.7 nm. Thickness is found to be critical on the materials and electron transport of In2O3. Controllable thickness of In2O3 at atomic scale enables the design of sufficient 2D carrier density in the In2O3 channel integrated with the conventional dielectric. The threshold voltage and channel carrier density are found to be considerably tuned by channel thickness. Such phenomenon is understood by the trap neutral level (TNL) model where the Fermi-l…
Palladium diselenide (PdSe2) is a recently isolated layered material that has attracted a lot of interest for the pentagonal structure, the air stability and the electrical properties largely tunable by the number of layers. In this work, PdSe2 is used in the form of multilayer as the channel of back-gate field-effect transistors, which are studied under repeated electron irradiations. Source-drain Pd leads enable contacts with resistance below 350 kOhm um. The transistors exhibit a prevailing n-type conduction in high vacuum, which reversibly turns into ambipolar electric transport at atmosph…
The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2/Vs in ambient conditions, which we attribute to the …
Single-electron effects have been widely investigated as a typical physical phenomenon in nanoelectronics. The single-electron effect caused by trap sites has been observed in many devices. In general, traps are randomly distributed and not controllable; therefore, different current--voltage characteristics are observed through traps even in silicon transistors having the same device parameters (e.g., gate length). This allows us to use single-electron effects as fingerprints of chips. In this study, we analyze the single-electron effect of traps in conventional silicon transistors and show th…
In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation.
Trapped fields of over 20 T are, in principle, achievable in bulk, single-grain high temperature cuprate superconductors. The principle barriers to realizing such performance are, firstly, the large tensile stresses that develop during the magnetization of such trapped-field magnets as a result of the Lorentz force, which lead to brittle fracture of these ceramic-like materials at high fields and, secondly, catastrophic thermal instabilities as a result of flux movement during magnetization. Moreover, for a batch of samples nominally fabricated identically, the statistical nature of the failur…
Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as gate insulator are being extensively explored as a promising device candidate for three-dimensional (3D) NAND memory application. FE HfO2 exhibits long retention over 10 years, high endurance over 1012 cycles, high speed with sub-ns polarization switching, and high remnant polarization of 10-30 μC/cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge bala…
We describe the use of laser-enhanced etching of fused silica in order to build multi-layer ion traps. This technique offers high precision of both machining and alignment of adjacent wafers. As examples of designs taking advantage of this possibility, we describe traps for realizing two key elements of scaling trapped ion systems. The first is a trap for a cavity-QED interface between single ions and photons, in which the fabrication allows shapes that provide good electro-static shielding of the ion from charge build-up on the mirror surfaces. The second incorporates two X-junctions allowing…
A memory window of ferroelectric field-effect transistors (FeFETs), defined as a separation of the HIGH-state and the LOW-state threshold voltages, is an important measure of the FeFET memory characteristics. In this study, we theoretically investigate the relation between the FeFET memory window and the P-E hysteresis loop of the ferroelectric gate insulator, and derive a compact model explicitly described by material parameters. It is found that the memory window is linearly proportional to the ferroelectric polarization for the small polarization regime, and converges to the limit value of …
We report a new approach to integrating high-\k{appa} dielectrics in both bottom- and top-gated MoS2 field-effect transistors (FETs) through thermal oxidation and mechanical assembly of layered twodimensional (2D) TaS2. Combined X-ray photoelectron spectroscopy (XPS), optical microscopy, atomic force microscopy (AFM), and capacitance-voltage (C-V) measurements confirm that multilayer TaS2 flakes can be uniformly transformed to Ta2O5 with a high dielectric constant of ~ 15.5 via thermal oxidation, while preserving the geometry and ultra-smooth surfaces of 2D TMDs. Top-gated MoS2 FETs fabricated…
Electrical characterization of few-layer MoS2 based field effect transistors with Ti/Au electrodes is performed in the vacuum chamber of a scanning electron microscope in order to study the effects of electron beam irradiation on the transport properties of the device. A negative threshold voltage shift and a carrier mobility enhancement is observed and explained in terms of positive charges trapped in the SiO2 gate oxide, during the irradiation. The transistor channel current is increased up to three order of magnitudes after the exposure to an irradiation dose of 100e-/nm2. Finally, a comple…
Atomically-thin 2D semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their full acceptance as compliant materials for integration in logic devices. Two key-components to master are the barriers at metal/semiconductor interfaces and the mobility of the semiconducting channel, which endow the building-blocks of ${pn}$ diode and field effect transistor. Here, we have devised a reverted stacking technique to intercalate a wrinkle-free h-BN tunnel …
