发表机构
Gwangju Institute of Science and Technology; Ulsan National Institute of Science and Technology; Aalto University; VTT Technical Research Centre of Finland Ltd.; Sungkyunkwan University; Korea Research Institute of Chemical Technology; OtaNano-Nanomicroscopy Center, Aalto University; Yonsei University; Beijing Institute of Technology; Nanyang Technological University; Arizona State University; Seoul National University; University of Cambridge（光州科学技术院; 蔚山科学技术院; 阿尔托大学; 芬兰技术研究中心有限公司; 成均馆大学; 韩国化学技术研究所; 阿尔托大学奥塔纳米显微镜中心; 延世大学; 北京理工大学; 南洋理工大学; 亚利桑那州立大学; 首尔国立大学; 剑桥大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文通过将拓扑绝缘体Bi2Se3表面转化为绝缘BiF3来工程化栅极侧屏蔽边界，尽管电容略有降低，但MoS2晶体管实现了近热离子开关和约七倍更低的漏致势垒降低，为晶体管静电控制提供了新设计维度。
AI 中文摘要
传统的栅极堆叠微缩通过降低介电层厚度并提高介电常数来实现，但通常将栅极侧屏蔽边界的位置和电子特性视为固定不变。然而，随着等效氧化层厚度的减小，有限的界面响应可能日益制约栅极控制能力[1-5]。本文表明，这一屏蔽边界本身可以通过将拓扑绝缘体Bi2Se3的表面转化为绝缘的高介电常数BiF3来进行工程调控。位置分辨计算揭示了在非晶BiF3/晶体Bi2Se3界面处立即出现带隙打开的界面，以及在相邻亚界面层中重构的带隙闭合的Bi2Se3衍生态，同时伴随局域界面偶极子。独立地，电容测量解析出一个有限的串联响应，与该埋藏边界的电子可压缩性一致，该响应降低了而非增强了标称堆叠电容。尽管存在这一电容代价，具有紧密匹配的BiF3厚度和共同的BiF3/MoS2沟道侧材料界面的MoS2晶体管表现出近热离子开关特性、可忽略的迟滞，以及比仅含BiF3的对照器件低约七倍的漏致势垒降低。这些结果确定了栅极侧屏蔽边界的位置和电子特性是超越标称介电电容的晶体管静电控制的额外设计变量。
英文摘要
Conventional gate-stack scaling reduces dielectric thickness and increases permittivity while largely treating the position and electronic character of the gate-side screening boundary as fixed. Here we show that this boundary can be engineered by converting the surface of the topological insulator Bi\textsubscript{2}Se\textsubscript{3} into insulating high-$κ$ BiF\textsubscript{3}. Position-resolved calculations reveal a gap-opened immediate amorphous-BiF\textsubscript{3}/crystalline-Bi\textsubscript{2}Se\textsubscript{3} interface and a reconstructed gap-closed Bi\textsubscript{2}Se\textsubscript{3}-derived state in the adjacent subinterface layer, accompanied by a localized interfacial dipole. Capacitor measurements independently resolve a finite series response consistent with electronic compressibility at this boundary; this response lowers the nominal stack capacitance. Despite this capacitance penalty, MoS\textsubscript{2} transistors with closely matched BiF\textsubscript{3} thicknesses and a common BiF\textsubscript{3}/MoS\textsubscript{2} channel-side material interface exhibit near-thermionic-limit switching, negligible hysteresis and substantially weaker subthreshold drain-bias dependence than BiF\textsubscript{3}-only controls. These results identify the position and electronic character of the gate-side screening boundary as additional design variables for transistor electrostatics beyond nominal dielectric capacitance.
Comments37 total pages, 24 main pages, 13 supplementary information pages, 4 main figures, 8 extended data figures, 2 extended data tables
