ESP4ML：基于平台的嵌入式机器学习片上系统设计
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning
摘要：
我们提出了ESP 4 ML，这是一个开源的系统级设计流程，用于为需要机器学习和信号处理算法的硬件加速的嵌入式应用构建和编程SoC架构。我们通过将两个已建立的开源项目（ESP和HLS 4 ML）合并到一个新的全自动设计流程中来实现ESP 4 ML。针对HLS 4 ML生成的加速器的SoC集成，设计了一套新的可通过高级综合进行综合的参数化接口电路。针对加速器的配置和管理，我们在Linux平台上开发了一个嵌入式软件运行时系统。有了这个硬件/软件层，我们解决了在片上网络上动态塑造数据流量的挑战，以激活和支持当前在SoC上运行的应用程序工作负载所需的加速器的可重新配置管道。我们展示了基于FPGA的完整SoC实例实现的垂直集成贡献，这些实例引导Linux并执行计算机-视觉应用程序，处理从谷歌街景数据库拍摄的图像。
英文摘要：
We present ESP4ML, an open-source system-level design flow to build and program SoC architectures for embedded applications that require the hardware acceleration of machine learning and signal processing algorithms. We realized ESP4ML by combining two established open-source projects (ESP and HLS4ML) into a new, fully-automated design flow. For the SoC integration of accelerators generated by HLS4ML, we designed a set of new parameterized interface circuits synthesizable with high-level synthesis. For accelerator configuration and management, we developed an embedded software runtime system on top of Linux. With this HW/SW layer, we addressed the challenge of dynamically shaping the data traffic on a network-on-chip to activate and support the reconfigurable pipelines of accelerators that are needed by the application workloads currently running on the SoC. We demonstrate our vertically-integrated contributions with the FPGA-based implementations of complete SoC instances booting Linux and executing computer-vision applications that process images taken from the Google Street View database.
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