SpiNNaker2芯片：用于灵活且可扩展的受脑启发计算的多核平台
The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing
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中文总结 AI 辅助
研究旨在借助SpiNNaker2芯片弥合深度网络与神经形态计算差距。核心方法是该芯片集成多种元件与接口。主要贡献为展示其在多种工作负载下的性能效率，支持大规模脉冲神经网络，且低功耗可探索多种计算模式，是通用硬件平台。
中文摘要 AI 辅助
在深度学习中，效率对于补偿模型规模和应用的持续增长愈发重要。长期以来，神经形态硬件一直被倡导为深度网络的未来替代方案，它从大脑获取灵感以实现前所未有的能源效率。然而，这些优势的展示直到最近才在复杂度和实际适用性方面有所增长。借助SpiNNaker2，我们推出了一款芯片，它弥合了深度网络与神经形态计算之间的差距，并允许灵活探索结合这两个领域的计算方法。它具有152个配备ARM M4F处理器和专用加速器的处理元件、用于可扩展基于事件通信的扩展SpiNNaker路由架构以及用于系统集成的一系列外部接口，包括千兆以太网和LPDDR4内存接口。我们展示了SpiNNaker2芯片在神经形态和深度网络工作负载以及新颖的基于事件计算方法方面的性能和效率。对于深度网络工作负载，该芯片在高性能模式下可达4.5 TOPS，在高效模式下对于INT8工作负载可达2.7 TOPS/W的效率。该芯片在以1 ms时间步长模拟时支持超过150000个神经元和超过18亿次突触事件/秒的脉冲神经网络。其低于250 mW的低基线功耗即使在不同工作负载条件下也能实现高效，从而允许探索稀疏和基于事件的计算模式。所有这些都证明了该芯片作为用于可扩展受脑启发计算及其与主流深度网络方法结合的通用硬件平台的能力。
英文摘要
In deep learning, efficiency gets more and more important to compensate for the ongoing growth in model sizes and applications. Neuromorphic hardware has long been advocated as an upcoming alternative to deep networks, taking inspiration from the brain for achieving unprecedented energy efficiency. However, demonstrations of these gains only recently began to grow in complexity and real-world applicability. With SpiNNaker2, we present a chip that bridges the gap between deep networks and neuromorphic computing and allows for flexible exploration of computing approaches that combine both worlds. It features 152 processing elements equipped with an ARM M4F processor and dedicated accelerators, an extended SpiNNaker routing fabric for scalable event-based communication and a range of external interfaces for system integration, including Gbit Ethernet and an LPDDR4 memory interface. We demonstrate performance and efficiency of the SpiNNaker2 chip for neuromorphic and deep network workloads, as well as novel event-based computing approaches. For deep network workloads, the chip achieves up to 4.5 TOPS in high performance mode and up to 2.7 TOPS/W efficiency in high efficiency mode for INT8 workloads. The chip supports spiking neural networks with >150000 neurons and >1.8 billion synaptic events/s when simulated with a 1 ms time step. Its low baseline power of less than 250 mW allows for efficiency even under varying workload conditions, allowing to explore sparse and event-based modes of computation. All this demonstrates the chip's capabilities as a universal hardware platform for scalable brain-inspired computing and its combinations with mainstream deep network approaches.
发表机构
- TU Dresden（德累斯顿工业大学）
机构由 AI 辅助整理，请以论文原文为准。
