Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result, low depth circuits such as quantum carry lookahead adders (QCLA)s have caught the attention of researchers. This work presents two QCLA designs each optimized with emphasis on T-count or qubit cost respectively. In-place and out-of-place versions of each design are shown. The proposed QCLAs are compared against the existing works in terms of T-count. The proposed QCLAs for out-of-place addition achieve average T gate savings of $54.34 \%$ and $37.21 \%$, respectively. The proposed QCLAs for in-place addition achieve average T gate savings of $72.11 \%$ and $35.87 \%$
We improve the Toffoli count of low depth quantum adders, and analyze how their spacetime cost reacts to having a limited number of magic state factories. We present a block lookahead adder that parallelizes across blocks of bits of size $b$, instead of over all bits. The block lookahead adder achieves a Toffoli count of $3n + 5n/b$ for out of place addition (vs $4n$ in previous work by Thapliyal et al) and $5n + 8n/b$ for in place addition (vs $7n$ in previous work by Thapliyal et al). The tradeoff is that the reaction depth of these circuits depends linearly on $b$, and they use additional w…
We present the design and evaluation of a quantum carry-lookahead adder (QCLA) using measurement-based quantum computation (MBQC), called MBQCLA. QCLA was originally designed for an abstract, concurrent architecture supporting long-distance communication, but most realistic architectures heavily constrain communication distances. The quantum carry-lookahead adder is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. MBQCLA utilizes MBQC's ability to transfer quantum states in unit time to accelerate addition. MBQCLA breaks the latency li…
Control modular addition is a core arithmetic function, and we must consider the computational cost for actual quantum computers to realize efficient implementation. To achieve a low computational cost in a control modular adder, we focus on minimizing KQ, defined by the product of the number of qubits and the depth of the circuit. In this paper, we construct an efficient control modular adder with small KQ by using relative-phase Toffoli gates in two major types of quantum computers: Fault-Tolerant Quantum Computers (FTQ) on the Logical layer and Noisy Intermediate-Scale Quantum Computers (NI…
Progress in quantum hardware design is progressing toward machines of sufficient size to begin realizing quantum algorithms in disciplines such as encryption and physics. Quantum circuits for addition are crucial to realize many quantum algorithms on these machines. Ideally, quantum circuits based on fault-tolerant gates and error-correcting codes should be used as they tolerant environmental noise. However, current machines called Noisy Intermediate Scale Quantum (NISQ) machines cannot support the overhead associated with faulttolerant design. In response, low depth circuits such as quantum c…
In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry $c_0$ and no ancilla input bits, and (ii) one with input carry $c_0$ and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay…
Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in t…
In this work, we propose an adder for the 2D NTC architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computat…
Reciprocal Quantum Logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2GHz. Latency is only 150 ps at a clock rate of 10GHz.
We present a paradigm for constructing approximate quantum circuits from reversible classical circuits that operate on many possible encodings of an input and send almost all encodings of that input to an encoding of the correct output. We introduce oblivious carry runways, which use piecewise addition circuits to perform approximate encoded additions and reduce the asymptotic depth of addition to $O(\lg \lg n)$. We show that the coset representation of modular integers (Zalka 2006) is an approximate encoded modular addition, and that it can be used in combination with oblivious carry runways.…
We optimize the area and latency of Shor's factoring while simultaneously improving fault tolerance through: (1) balancing the use of ancilla generators, (2) aggressive optimization of error correction, and (3) tuning the core adder circuits. Our custom CAD flow produces detailed layouts of the physical components and utilizes simulation to analyze circuits in terms of area, latency, and success probability. We introduce a metric, called ADCR, which is the probabilistic equivalent of the classic Area-Delay product. Our error correction optimization can reduce ADCR by an order of magnitude or m…
Qutrit (or ternary) structures arise naturally in many quantum systems, particularly in certain non-abelian anyon systems. We present efficient circuits for ternary reversible and quantum arithmetics. Our main result is the derivation of circuits for two families of ternary quantum adders, namely ripple carry adders and carry look-ahead adders. The main difference to the binary case is the more complicated form of the ternary carry, which leads to higher resource counts for implementations over a universal ternary gate set. Our ternary ripple adder circuit has a circuit depth of $O(n)$ and use…
We construct a self-correcting CCZ state (the "AutoCCZ") with embedded delayed choice CZs for completing gate teleportations. Using the AutoCCZ state we create efficient surface code spacetime layouts for both a depth-limited circuit (a ripply-carry addition) and a Clifford-limited circuit (a QROM read). Our layouts account for distillation and routing, are based on plausible physical assumptions for a large-scale superconducting qubit platform, and suggest that circuit-level Toffoli parallelism (e.g. using a carry-lookahead adder instead of a ripple-carry adder) will not reduce the execution …
Shanghai University（上海大学）；University of the Basque Country UPV/EHU（巴斯克地区大学）；IKERBASQUE, Basque Foundation for Science（巴斯克科学基金会）
Quantum autoencoders allow for reducing the amount of resources in a quantum computation by mapping the original Hilbert space onto a reduced space with the relevant information. Recently, it was proposed to employ approximate quantum adders to implement quantum autoencoders in quantum technologies. Here, we carry out the experimental implementation of this proposal in the Rigetti cloud quantum computer employing up to three qubits. The experimental fidelities are in good agreement with the theoretical prediction, thus proving the feasibility to realize quantum autoencoders via quantum adders …
We provide evidence that commonly held intuitions when designing quantum circuits can be misleading. In particular we show that: a) reducing the T-count can increase the total depth; b) it may be beneficial to trade CNOTs for measurements in NISQ circuits; c) measurement-based uncomputation of relative phase Toffoli ancillae can make up to 30\% of a circuit's depth; d) area and volume cost metrics can misreport the resource analysis. Our findings assume that qubits are and will remain a very scarce resource. The results are applicable for both NISQ and QECC protected circuits. Our method uses …
A rotation-based synthesis framework for reversible logic is proposed. We develop a canonical representation based on binary decision diagrams and introduce operators to manipulate the developed representation model. Furthermore, a recursive functional bi-decomposition approach is proposed to automatically synthesize a given function. While Boolean reversible logic is particularly addressed, our framework constructs intermediate quantum states that may be in superposition, hence we combine techniques from reversible Boolean logic and quantum computation. The proposed approach results in quadra…
Generic quantum-circuit simulation appears intractable for conventional computers and may be unnecessary because useful quantum circuits exhibit significant structure that can be exploited during simulation. For example, Gottesman and Knill identified an important subclass, called stabilizer circuits, which can be simulated efficiently using group-theory techniques and insights from quantum physics. Realistic circuits enriched with quantum error-correcting codes and fault-tolerant procedures are dominated by stabilizer subcircuits and contain a relatively small number of non-Clifford component…
