Agung Trisetyarso, Rodney Van Meter, Kohei M. Itoh
We present the design of a quantum carry-lookahead adder using measurement-based quantum computation. The quantum carry-lookahead adder (QCLA) is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. Our design is evaluated in terms of number of time steps and the total number of qubits used.
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Quantum adders: on the structural link between the ripple-carry and carry-lookahead techniques
该研究基于Toffoli梯的三种实现方式与量子加法器的两种基础结构，推导出六种量子加法器（含两种新设计），其中一种新型超前进位加法器性能更优，揭示了两类加法器设计的结构关联。
We improve the Toffoli count of low depth quantum adders, and analyze how their spacetime cost reacts to having a limited number of magic state factories. We present a block lookahead adder that parallelizes across blocks of bits of size $b$, instead of over all bits. The block lookahead adder achieves a Toffoli count of $3n + 5n/b$ for out of place addition (vs $4n$ in previous work by Thapliyal et al) and $5n + 8n/b$ for in place addition (vs $7n$ in previous work by Thapliyal et al). The tradeoff is that the reaction depth of these circuits depends linearly on $b$, and they use additional w…
We present an efficient addition circuit, borrowing techniques from the classical carry-lookahead arithmetic circuit. Our quantum carry-lookahead (QCLA) adder accepts two n-bit numbers and adds them in O(log n) depth using O(n) ancillary qubits. We present both in-place and out-of-place versions, as well as versions that add modulo 2^n and modulo 2^n - 1. Previously, the linear-depth ripple-carry addition circuit has been the method of choice. Our work reduces the cost of addition dramatically with only a slight increase in the number of required qubits. The QCLA adder can be used within curre…
We present the design of a quantum carry-lookahead adder using measurement-based quantum computation. QCLA utilizes MBQC`s ability to transfer quantum states in unit time to accelerate addition. The quantum carry-lookahead adder (QCLA) is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. QCLA is an order of magnitude faster than a ripple-carry adder when adding registers longer than 100 qubits but requires a cluster state that is an order of magnitude larger. Hand optimization results in a $\approx$ 26% reduction in spatial resources fo…
Control modular addition is a core arithmetic function, and we must consider the computational cost for actual quantum computers to realize efficient implementation. To achieve a low computational cost in a control modular adder, we focus on minimizing KQ, defined by the product of the number of qubits and the depth of the circuit. In this paper, we construct an efficient control modular adder with small KQ by using relative-phase Toffoli gates in two major types of quantum computers: Fault-Tolerant Quantum Computers (FTQ) on the Logical layer and Noisy Intermediate-Scale Quantum Computers (NI…
A Higher Radix Architecture for Quantum Carry-lookahead Adder
本文提出一种基于高基数结构的量子超前进位加法器，通过引入高基数层优化量子比特数、T门数量和T深度，在性能上优于现有量子超前进位加法器及Draper out-of-place加法器。
We present the design and evaluation of a quantum carry-lookahead adder (QCLA) using measurement-based quantum computation (MBQC), called MBQCLA. QCLA was originally designed for an abstract, concurrent architecture supporting long-distance communication, but most realistic architectures heavily constrain communication distances. The quantum carry-lookahead adder is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. MBQCLA utilizes MBQC's ability to transfer quantum states in unit time to accelerate addition. MBQCLA breaks the latency li…
A New Method For Manipulating Circuits, Application To Quantum Adders
提出操控受控量子电路的新技术，实现基于量子傅里叶变换与纹波进位技术的量子加法器间的门级转译，并设计一种无辅助比特的先行进位量子加法器。
Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result,…
In this paper, two quantum networks for the addition operation are presented. One is the Modified Quantum Plain (MQP) adder, and the other is the Quantum Carry Look-Ahead (QCLA) adder. The MQP adder is obtained by modifying the Conventional Quantum Plain (CQP) adder. The QCLA adder is an extension of conventional digital Carry Look-Ahead adder. Compared with the CQP adder, two main advantages are as follows: First, the proposed MQP and QCLA adders have less number of elementary gates than the CQP adder. Secondly, the number of processing stages of the MQP and QCLA adder are less than ones of t…
Progress in quantum hardware design is progressing toward machines of sufficient size to begin realizing quantum algorithms in disciplines such as encryption and physics. Quantum circuits for addition are crucial to realize many quantum algorithms on these machines. Ideally, quantum circuits based on fault-tolerant gates and error-correcting codes should be used as they tolerant environmental noise. However, current machines called Noisy Intermediate Scale Quantum (NISQ) machines cannot support the overhead associated with faulttolerant design. In response, low depth circuits such as quantum c…
A Logarithmic Depth Quantum Carry-Lookahead Modulo $(2^n-1)$ Adder
本文提出量子先行进位模 $(2^n-1)$ 加法器QCLMA，通过树结构进位路径将深度从O(n)降至O(log n)，并在IBM Cairo上实现QSFR提升47.21%，以增强NISQ设备上的噪声保真度。
Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in t…
We present a new linear-depth ripple-carry quantum addition circuit. Previous addition circuits required linearly many ancillary qubits; our new adder uses only a single ancillary qubit. Also, our circuit has lower depth and fewer gates than previous ripple-carry adders.
We present a paradigm for constructing approximate quantum circuits from reversible classical circuits that operate on many possible encodings of an input and send almost all encodings of that input to an encoding of the correct output. We introduce oblivious carry runways, which use piecewise addition circuits to perform approximate encoded additions and reduce the asymptotic depth of addition to $O(\lg \lg n)$. We show that the coset representation of modular integers (Zalka 2006) is an approximate encoded modular addition, and that it can be used in combination with oblivious carry runways.…
In this work, we propose an adder for the 2D NTC architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computat…
Optimizing T and CNOT Gates in Quantum Ripple-Carry Adders and Comparators
本文优化了量子纹波进位加法器和比较器中的T门与CNOT门，在Clifford+T门集下实现了T深度3n和CNOT深度8n，显著优于原始电路的6n T深度。
Reciprocal Quantum Logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2GHz. Latency is only 150 ps at a clock rate of 10GHz.
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing
本文面向 NISQ 量子计算提出五种抗噪声且降低深度的近似量子加法器设计，利用直通和单 CNOT 门等低深度方案，在 IBM Qiskit 噪声实验中显著提升保真度。
Resource analysis of Shor's elliptic curve algorithm with an improved quantum adder on a two-dimensional lattice
本研究提出一种深度最优且空间高效的量子加法器，并基于二维格点架构对Shor椭圆曲线算法进行资源分析，表明破解NIST P-256约需4300个逻辑量子比特，为量子密码分析提供新基准。
Construction of Boolean Logic Gates Using QFT-Based Adder Architecture
本研究利用基于量子傅里叶变换的加法器电路，通过预处理和后处理构造了五种布尔逻辑门的量子可逆对应物，在输入增加时减少了量子比特数。
In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry $c_0$ and no ancilla input bits, and (ii) one with input carry $c_0$ and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay…
Below-threshold execution of fault-tolerant ripple-carry addition on a trapped-ion quantum computer
该研究在Quantinuum的Helios-1囚禁离子量子计算机上，结合检错码与算法校验实现容错行波进位加法，使1位加法逻辑失败率大幅降低，多位加法器性能提升，长加法器达阈值以上执行。
Scalable Quantum Reversible BCD Adder Architectures with Enhanced Speed and Reduced Quantum Cost for Next-Generation Computing
本文提出两种优化延迟和量子成本的可逆BCD加法器设计，通过进位跳过技术提升性能，适用于下一代量子计算系统。
Tradeoff between noise and banding in a quantum adder with qudits
本文研究任意维度量子加法器的资源需求，证明受控旋转门数量上界，并揭示噪声下带状限制使恒定深度近似电路更优，同时提出用一维自旋链实现量子加法的方案。
The PPKN Gate: An Optimal 1-Toffoli Input-Preserving Full Adder for Quantum Arithmetic
本文提出PPKN门，通过仅使用一个TOFFOLI门和五个CNOT门实现输入保持功能，相较于HNG门在量子成本和逻辑深度上更优，并提出模块化构建n位加法器的架构。
Optimal Toffoli-Depth Quantum Adder
本文通过探索 160 种进位传播结构组合，证明量子加法器可实现 log n + O(1) 的最优 Toffoli 深度，较现有最佳电路降低近 50%，并给出理论分析与仿真验证。
Quantum autoencoders allow for reducing the amount of resources in a quantum computation by mapping the original Hilbert space onto a reduced space with the relevant information. Recently, it was proposed to employ approximate quantum adders to implement quantum autoencoders in quantum technologies. Here, we carry out the experimental implementation of this proposal in the Rigetti cloud quantum computer employing up to three qubits. The experimental fidelities are in good agreement with the theoretical prediction, thus proving the feasibility to realize quantum autoencoders via quantum adders …
Quantum Multiplier Based on Exponent Adder
提出 QMbead 量子乘法器，通过指数编码、叠加态制备与量子加法实现整数或十进制数相乘，仅需 log_2(n) 个核心量子比特，并在模拟器上以 17 量子比特完成 273 位乘法。
Qutrit (or ternary) structures arise naturally in many quantum systems, particularly in certain non-abelian anyon systems. We present efficient circuits for ternary reversible and quantum arithmetics. Our main result is the derivation of circuits for two families of ternary quantum adders, namely ripple carry adders and carry look-ahead adders. The main difference to the binary case is the more complicated form of the ternary carry, which leads to higher resource counts for implementations over a universal ternary gate set. Our ternary ripple adder circuit has a circuit depth of $O(n)$ and use…
Truncated phase-based quantum arithmetic: error propagation and resource reduction
本文提出一种改进的Draper量子加法器，通过将小角度旋转截断到粗粒度水平并配合策略性修正来降低硬件资源需求，在Shor算法分解RSA-2048场景中证明可将量子傅里叶变换截断至π/64，并量化了逻辑资源与魔法态的节省。
Ancilla-free Quantum Adder with Sublinear Depth
本研究提出首个无辅助比特的亚线性深度精确量子加法器，基于经典可逆逻辑优化CNOT与Toffoli阶梯算子深度，实现n位数加法深度O(log²n)，并给出量子寄存器递增与加常数的新构造。
We provide evidence that commonly held intuitions when designing quantum circuits can be misleading. In particular we show that: a) reducing the T-count can increase the total depth; b) it may be beneficial to trade CNOTs for measurements in NISQ circuits; c) measurement-based uncomputation of relative phase Toffoli ancillae can make up to 30\% of a circuit's depth; d) area and volume cost metrics can misreport the resource analysis. Our findings assume that qubits are and will remain a very scarce resource. The results are applicable for both NISQ and QECC protected circuits. Our method uses …
Towards Deploying Optimistic Quantum Fourier Transforms: An Architecture-Algorithm Co-Design Study
本文研究了在可重构中性原子硬件上基于表面码容错执行模型的乐观量子傅里叶变换架构-算法协同设计，提出热区架构以动态路由资源包，分析不同热区数量对并行性和延迟的影响，并识别算法-架构瓶颈。
Quantum hardware noise learning via differentiable Kraus representation on tensor networks
本文提出通过可微Kraus算符学习量子硬件噪声，利用矩阵乘积密度算符模型模拟电路，并在IBM Fez处理器上验证了方法的有效性，展示了其在不同电路中的泛化能力。
Quantum Circuit Realization and Grover Cryptanalysis of the Hybrid ARX-SPN Cipher GFSPX
针对轻量级分组密码GFSPX，提出量子电路优化实现并利用Grover算法进行密钥恢复攻击，评估其量子安全性。
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