arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2001.07427cond-mat.mes-hall
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四维拓扑绝缘体的电路实现

Circuit Implementation of a Four-Dimensional Topological Insulator

You Wang, Hannah M. Price, Baile Zhang, Y. D. Chong

摘要:

拓扑绝缘体的分类预测了高维拓扑相的存在,这些相在真实材料中不可能出现,因为这些相限于三个或更少的空间维度。我们使用电路来实验性地实现四维(4D)拓扑格。晶格维数是由电路连接建立的,而不是通过映射到一个低维系统。在晶格的三维表面上,我们观察到与非零的第二陈数,但消失的第一陈数相关联的拓扑表面状态。4D晶格属于对称类AI,它指的是没有特殊空间对称性的时间反演不变和无自旋系统。AI类在一到三个空间维度上是拓扑平凡的,因此4D是在该类中实现拓扑绝缘体的最低可能维度。这项工作铺平了道路,使用电路探索高维拓扑模型。

英文摘要:

The classification of topological insulators predicts the existence of high-dimensional topological phases that cannot occur in real materials, as these are limited to three or fewer spatial dimensions. We use electric circuits to experimentally implement a four-dimensional (4D) topological lattice. The lattice dimensionality is established by circuit connections, and not by mapping to a lower-dimensional system. On the lattice's three-dimensional surface, we observe topological surface states that are associated with a nonzero second Chern number but vanishing first Chern numbers. The 4D lattice belongs to symmetry class AI, which refers to time-reversal-invariant and spinless systems with no special spatial symmetry. Class AI is topologically trivial in one to three spatial dimensions, so 4D is the lowest possible dimension for achieving a topological insulator in this class. This work paves the way to the use of electric circuits for exploring high-dimensional topological models.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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