Quantum computers based on superconducting circuits are experiencing a rapid development, aiming at outperforming classical computers in certain useful tasks in the near future. However, the currently available chip fabrication technologies limit the capability of gathering a large number of high-quality qubits in a single superconducting chip, a requirement for implementing quantum error correction. Furthermore, achieving high connectivity in a chip poses a formidable technological challenge. Here, we propose a hybrid digital-analog quantum algorithm that enhances the physical connectivity among qubits coupled by an arbitrary inhomogeneous nearest-neighbour Ising Hamiltonian and generates an arbitrary all-to-all Ising Hamiltonian only by employing single-qubit rotations. Additionally, we optimize the proposed algorithm in the number of analog blocks and in the time required for the simulation. These results take advantage of the natural evolution of the system by combining the flexibility of digital steps with the robustness of analog quantum computing, allowing us to improve the connectivity of the hardware and the efficiency of quantum algorithms.
We evaluate the performance of small error-correcting codes, which we tailor to hardware platforms of very different connectivity and coherence: on a superconducting processor based on transmon qubits and a spintronic quantum register consisting of a nitrogen-vacancy center in diamond. Taking the hardware-specific errors and connectivity into account, we investigate the dependence of the resulting logical error rate on the platform features such as the native gates, native connectivity, gate times, and coherence times. Using a standard error model parameterized for the given hardware, we simul…
Pegasus is a graph which offers substantially increased connectivity between the qubits of quantum annealing hardware compared to the graph Chimera. It is the first fundamental change in the connectivity graph of quantum annealers built by D-Wave since Chimera was introduced in 2009 and then used in 2011 for D-Wave's first commercial quantum annealer. In this article we describe an algorithm which defines the connectivity of Pegasus and we provide what we believe to be the best way to graphically visualize Pegasus in order to see which qubits couple to each other. As supplemental material, we …
The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurem…
Quantum circuit Born machines (QCBMs) and training via variational quantum algorithms (VQAs) are key applications for near-term quantum hardware. QCBM ansätze designs are unique in that they do not require prior knowledge of a physical Hamiltonian. Many ansätze are built from fixed designs. In this work, we train and compare the performance of QCBM models built using two commonly employed parameterizations and two commonly employed entangling layer designs. In addition to comparing the overall performance of these models, we look at features and characteristics of the loss landscape -- connect…
Due to several physical limitations in the realisation of quantum hardware, today's quantum computers are qualified as Noisy Intermediate-Scale Quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realisations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbour connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual…
Institute of Artificial Intelligence, Hefei Comprehensive National Science Center（人工智能研究院，合肥综合性国家科学中心）；Laboratory of Quantum Information, University of Science and Technology of China（中国科学技术大学量子信息实验室）；Anhui Province Key Laboratory of Quantum Network, University of Science and Technology of China（中国科学技术大学安徽省量子网络重点实验室）；Origin Quantum Computing（本源量子计算）
We focus on the depth optimization of CNOT circuits on hardwares with limited connectivity. We adapt the algorithm from Kutin et al. that implements any $n$-qubit CNOT circuit in depth at most $5n$ on a Linear Nearest Neighbour (LNN) architecture. Our proposal is a block version of Kutin et al.'s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have the less the depth. We derive better theoretical upper bounds and we provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on so…
Hardware-Aware Fermion-to-Qubit Mappings for Simulating the 2D Hubbard Model on Heavy-Hexagon Quantum Processors
University of Milano-Bicocca（米兰比可卡大学）；INFN Milano-Bicocca（意大利国家核物理研究所米兰比可卡分部）；Bicocca Quantum Technologies (BiQuTe) Centre（比可卡量子技术中心）；University of Helsinki（赫尔辛基大学）；HUN-REN Wigner Research Centre for Physics（匈牙利研究与教育网络维格纳物理研究中心）；Algorithmiq Ltd（算法有限公司）；University of Florence（佛罗伦萨大学）；INFN Firenze（意大利国家核物理研究所佛罗伦萨分部）
Quantum computing hardware is undergoing rapid development from proof-of-principle devices to scalable machines that could eventually challenge classical supercomputers on specific tasks. On platforms with local connectivity, the transition from one- to two-dimensional arrays of qubits is seen as a natural technological step to increase the density of computing power and to reduce the routing cost of limited connectivity. Here we map and schedule representative algorithmic workloads - the Quantum Fourier Transform (QFT) relevant to factoring, the Grover diffusion operator relevant to quantum s…
A primary objective of quantum computation is to efficiently simulate quantum physics. Scientifically and technologically important quantum Hamiltonians include those with spin-$s$, vibrational, photonic, and other bosonic degrees of freedom, i.e. problems composed of or approximated by $d$-level particles (qudits). Recently, several methods for encoding these systems into a set of qubits have been introduced, where each encoding's efficiency was studied in terms of qubit and gate counts. Here, we build on previous results by including effects of hardware connectivity. To study the number of S…
The recent availability of quantum annealers has fueled a new area of information technology where such devices are applied to address practically motivated and computationally difficult problems with hardware that exploits quantum mechanical phenomena. D-Wave annealers are promising platforms to solve these problems in the form of quadratic unconstrained binary optimization. Here we provide a formulation of the Chinese postman problem that can be used as a tool for probing the local connectivity of graphs and networks. We treat the problem classically with a tabu algorithm and using a D-Wave …
High-connectivity circuits are a major roadblock for current quantum hardware. We propose a hybrid classical-quantum algorithm to simulate such circuits without swap-gate ladders. As main technical tool, we introduce quantum-classical-quantum interfaces. These replace an experimentally problematic gate (e.g. a long-range one) by single-qubit random measurements followed by state-preparations sampled according to a classical quasi-probability simulation of the noiseless gate. Each interface introduces a multiplicative statistical overhead which is remarkably independent of the on-chip qubit dis…
Currently available quantum computing hardware platforms have limited 2-qubit connectivity among their addressable qubits. In order to run a generic quantum algorithm on such a platform, one has to transform the initial logical quantum circuit describing the algorithm into an equivalent one that obeys the connectivity restrictions. In this work we construct a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by $\{\text{CNOT},R_{Z}\}$ and outputs a circuit that respects the connectivity of the device. As a concrete appli…
Programmable quantum systems based on Rydberg atom arrays have recently been used for hardware-efficient tests of quantum optimization algorithms [Ebadi et al., Science, 376, 1209 (2022)] with hundreds of qubits. In particular, the maximum independent set problem on so-called unit-disk graphs, was shown to be efficiently encodable in such a quantum system. Here, we extend the classes of problems that can be efficiently encoded in Rydberg arrays by constructing explicit mappings from a wide class of problems to maximum weighted independent set problems on unit-disk graphs, with at most a quadra…
We run a selection of algorithms on two state-of-the-art 5-qubit quantum computers that are based on different technology platforms. One is a publicly accessible superconducting transmon device with limited connectivity, and the other is a fully connected trapped-ion system. Even though the two systems have different native quantum interactions, both can be programmed in a way that is blind to the underlying hardware, thus allowing the first comparison of identical quantum algorithms between different physical systems. We show that quantum algorithms and circuits that employ more connectivity …
Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardw…
It is not currently known if quantum Turing machines can efficiently simulate probabilistic computations in the space-bounded case. In this paper we show that space-bounded quantum Turing machines can efficiently simulate a limited class of random processes: random walks on undirected graphs. By means of such simulations, it is demonstrated that the undirected graph connectivity problem for regular graphs can be solved by one-sided error quantum Turing machines that run in logspace and halt absolutely. It follows that symmetric logspace is contained in the quantum analogue of randomized logspa…
As quantum hardware increases in complexity, successful algorithmic execution relies more heavily on awareness of existing device constraints. In this work we focus on the problem of routing quantum information across the machine to overcome the limited connectivity of quantum hardware. Previous approaches address the problem for each two-qubit gate separately and then impose the compatibility of the different routes. Here we shift the focus onto the set of all routing operations that are possible at any given time and favor those that most benefit the global pattern of two-qubit gates. We ben…
Application-inspired benchmarks measure how well a quantum device performs meaningful calculations. In the case of parameterized circuit training, the computational task is the preparation of a target quantum state via optimization over a loss landscape. This is complicated by various sources of noise, fixed hardware connectivity, and for generative modeling, the choice of target distribution. Gradient-based training has become a useful benchmarking task for noisy intermediate scale quantum computers because of the additional requirement that the optimization step uses the quantum device to es…
Quantum annealing is a promising technique which leverages quantum mechanics to solve hard optimization problems. Considerable progress has been made in the development of a physical quantum annealer, motivating the study of methods to enhance the efficiency of such a solver. In this work, we present a quantum annealing approach to measure similarity among molecular structures. Implementing real-world problems on a quantum annealer is challenging due to hardware limitations such as sparse connectivity, intrinsic control error, and limited precision. In order to overcome the limited connectivit…
Quantum LDPC codes may provide a path to build low-overhead fault-tolerant quantum computers. However, as general LDPC codes lack geometric constraints, naïve layouts couple many distant qubits with crossing connections which could be hard to build in hardware and could result in performance-degrading crosstalk. We propose a 2D layout for quantum LDPC codes by decomposing their Tanner graphs into a small number of planar layers. Each layer contains long-range connections which do not cross. For any CSS code with a degree-$δ$ Tanner graph, we design stabilizer measurement circuits with depth at…
