130 MS/s 10位异步SAR ADC，带55.2 dB SNDR
A 130-MS/s 10-Bit Asynchronous SAR ADC with 55.2 dB SNDR
摘要：
介绍了一种采用90 nm CMOS工艺实现的低功耗10位130 MS/s逐次逼近型模数转换器（SAR ADC）。该异步ADC由一个比较器、SAR逻辑模块和两个用于容性数模转换器（DAC）的控制模块组成。在1.2 V电源电压和130 MS/s时，ADC的SNDR为55.2 dB，功耗为860 uW，品质因数（FOM）为50.9 fJ/MHz。该器件的有效位为8.8位，差分输入范围为1570 mV。
英文摘要：
This paper presents a low-power 10-bit 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 90 nm CMOS process. The proposed asynchronous ADC consists of a comparator, SAR logic block and two control blocks for the capacitive digital to analog converters (DAC). At a 1.2 V supply and 130 MS/s, the ADC achieves an SNDR of 55.2 dB and consumes 860 uW, resulting in a figure of merit (FOM) of 50.9 fJ/MHz. It achieves an ENOB of 8.8 bits with a differential input range of 1570 mV.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
