发表机构
Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China; Hamburg University of Technology（电子科技大学集成电路与系统研究所; 汉堡工业大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出一种对时序误差具有固有鲁棒性的频率交织ADC，通过嵌入式模拟傅里叶变换实现精确通道间距，在10位13GS/s下实现45.8dB SNDR和56.1dB SFDR，功耗26.4mA，Walden FoM为12.7 fJ/转换步。
AI 中文摘要
时序误差是高速模数转换器（ADC）中的一项基本挑战。本文提出了一种对时序误差具有固有鲁棒性的频率交织架构。频率交织通过嵌入式模拟傅里叶变换（AFT）实现，从而允许精确的通道间距。基于电荷的无源AFT能够与后续数据转换的电容式DAC共享电容阵列。本文提出了一种用于AFT矩阵中复值无理系数的电路实现，该实现消除了由器件比率引起的系统误差。在10位13GS/s下测量，该无校准ADC在奈奎斯特频率处实现了45.8dB的SNDR和56.1dB的SFDR。该ADC在单1V电源下消耗26.4mA电流，从而实现了12.7 fJ/转换步的Walden品质因数。
英文摘要
Timing errors represent a fundamental challenge in high-speed analog-to-digital converters (ADCs). This paper presents a frequency-interleaved architecture with inherent robustness to timing errors. The frequency interleaving is achieved by an embedded analog Fourier transform (AFT), allowing accurate channel spacing. The charge-based passive AFT is able to share the capacitor array with the capacitive DAC of the subsequent data conversion. A circuit implementation for the complex-valued irrational coefficients in the AFT matrix is proposed, which eliminates the device-ratio-induced systematic errors. Measured at 10b 13GS/s, the calibration-free ADC achieves 45.8-dB SNDR and 56.1-dB SFDR at Nyquist. The ADC consumes 26.4mA from a single 1V supply, resulting in a Walden FoM of 12.7 fJ/conv.-step.
