一种用于ADC串行链路解调器的低功耗20 Gb/s离散时间模拟前端
A Low-Power 20-Gb/s Discrete-Time Analog Front-End for ADC-Based Serial Link Equalizers
摘要：
本文提出了一种用于基于模数转换器（ADC）的均衡器的离散时间模拟前端。前端采用离散时间线性均衡器（DTLE）和超低功耗4位时间交错电荷控制闪存ADC。DTLE有两个功能：线性均衡以及采样和保持，用于后续电荷控制ADC。ADC采用全差分低功耗时钟比较器。通过在电荷导引前置放大器的内核中嵌入动态锁存器，实现了比较器的低功耗。20 Gb/s前端的设计和模拟在65 nm CMOS工艺。闪存ADC采用4级交错，因此需要4个DTLE以5 Gb/s的速度运行。5 Gb/s DTLE采用1.2 V电源供电时功耗为0.57 mW，ADC采用1 V电源供电时功耗为15.5 mW（20 GS/s），总功耗为17.78 mW或0.89 pJ/bit。对于频率为9.84 GHz、幅度为600 mVdiff的正弦输入，该ADC的SNDR为23.9 dB，SFDR为33.6 dB，有效位数（ENOB）为3.67位。
英文摘要：
This paper presents a discrete-time analog frontend for an analog-to-digital (ADC) based equalizers. The frontend uses a discrete-time linear equalizer (DTLE) and ultralow-power 4-bit time-interleaved charge-steering flash ADC. The DTLE serves two functions; linear equalization and sampling and holding for the following charge-steering ADC. The ADC uses fully differential low-power clocked comparators. Low power in the comparators is achieved by embedding a dynamic latch into the core of a charge-steering pre-amplifier. The 20-Gb/s front-end is designed and simulated in 65-nm CMOS technology. The flash ADC uses 4-stage interleaving and thus requires 4 DTLEs running at 5 Gb/s. A 5-Gb/s DTLE consumes 0.57 mW from a 1.2-V supply and the ADC consumes 15.5 mW from a 1-V supply at 20 GS/s for a total power dissipation of 17.78 mW or 0.89 pJ/bit. The ADC has an SNDR of 23.9 dB, an SFDR of 33.6 dB, and an effective number of bits (ENOB) of 3.67 bits for a sinusoidal input of frequency 9.84 GHz and amplitude 600 mVdiff .
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
