In this paper, we apply the sorting network theory to construct an analog rank order filter. We present a voltage mode CMOS two-input sorting element and arrange these to form a rank order filter. The resulting circuit is simpleand is a high-speed, high-precision design. Although the transistor count is moderately higher than other designs, the proposed circuit simultaneously outputs signals of all ranks rather than of just one specified rank. We also develop a slightly modified design which calculates the rank of a given signal. We present reports of simulations to verify the performance of the device.
We report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35um CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that…
High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardw…
The RD50-CMOS group aims to design and study High Voltage CMOS (HVCMOS) chips for use in a high radiation environment. Currently, measurements are performed on RD50-MPW2 chip, the second prototype developed by this group. The active matrix of the prototype consists of 8x8 pixels with analog front end. Details of the analog front end and simulations have been already published earlier. This contribution focuses on the Caribou based readout system of the active matrix. Each pixel of the active matrix can be readout one after the other. Relevant aspects of hardware, firmware and software are intr…
Depleted monolithic CMOS active pixel sensors (DMAPS) have been developed in order to demonstrate their suitability as pixel detectors in the outer layers of a toroidal LHC apparatus inner tracker (ATLAS ITk) pixel detector in the high-luminosity large hadron collider (HL-LHC). Two prototypes have been fabricated using 150 nm CMOS technology on high resistivity (> 2 k$Ω$ $cm^2$) wafers. The chip size is equivalent to that of the current ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and the analog readout of the DMAPS. The other is …
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measur…
CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel …
The CERN-RD50 CMOS working group develops the RD50-MPWseries of monolithic high-voltage CMOS pixel sensors for potential use in future high luminosity experiments such as the HL-LHC and FCC-hh. In this contribution, the design of the latest prototype in this series, RD50-MPW3, is presented. An overview of its pixel matrix and digital readout periphery is given, with discussion of the new structures implemented in the chip and the problems they aim to solve. The main analog and digital features of the sensor are already tested and initial laboratory characterisation of the chip is presented.
Purpose: CMOS pixel sensors have become extremely attractive for future high performance tracking devices. Initial R\&D work has been conducted for the vertex detector for the proposed Circular Electron Positron Collider that will allow precision Higgs measurements. It is critical to achieve low power consumption to minimize the material budget. This requires careful optimization of the sensor diode geometry to reach high charge-over-capacitance that allows reduction in analog power consumption. Methods: The electrode area and footprint are two critical elements in sensor diode geometry and ha…
In view of the tracking detector application to the ATLAS High Luminosity LHC (HL-LHC) upgrade, we have developed a new generation of High Voltage CMOS (HV-CMOS) monolithic pixel-sensor prototypes featuring the AMS aH18 (180 nm) commercial CMOS technology. By fully integrating both analog and digital readout-circuitry on the same particle-detecting substrate, current challenges of hybrid sensor technologies, i.e., larger readout input-capacitance, lower production-yield, and higher production and integration cost, can be downscaled. The large electrode design using high-resistivity substrates …
Influence of Radiation and AC Coupling on Time Performance of Analog Pixels Test Structures in 65 nm CMOS technology
European Organisation for Nuclear Research (CERN)（欧洲核子研究组织）；University of Torino（都灵大学）；INFN, Sezione di Torino（意大利国家核物理研究所都灵分部）；INFN, Sezione di Trieste（意大利国家核物理研究所的里雅斯特分部）；University of Bari（巴里大学）；INFN, Sezione di Bari（意大利国家核物理研究所巴里分部）；Polytechnic of Bari（巴里理工大学）；University of Trieste（的里雅斯特大学）
This paper presents a new auto zeroing technique that combines very high-speed operation, low power consumption, and low input switching interferences. This technique has been applied to the design of CMOS flash Analog-to-Digital converter for Ultra-Wide Band applications. This project is dealt with the design of an auto zeroing amplifier with three stages. It has to be operating on 1.2 power supply voltage and the input voltage is limited to 400 mv in 130 nm CMOS technology. The CMOS auto zeroing amplifier stages are simulated in the Advanced Design System (ADS) Tool.
Pixel sensors based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the outer layer of the ATLAS inner tracker upgrade at the High Luminosity LHC. Here, charged particles are detected using deep n-wells as sensor diodes with the depleted region extending into the silicon bulk. Both analog and digital readout electronics can be added to achieve different levels of integration up to a fully monolithic sensor. Small scale prototypes using the ams CMOS technology have previously demonstrated that it can achieve the required radiation toleran…
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also prese…
Test-beam results from MiniCACTUS-v2: A depleted monolithic CMOS timing sensor prototype
Institute for High Energy Physiscs (IFAE) Campus Autonomous University of Barcelona (UAB)（巴塞罗那自治大学高能物理研究所）；Autonomous University of Barcelona (UAB)（巴塞罗那自治大学）；Catalan Institution for Research and Advanced Studies (ICREA)（加泰罗尼亚研究与高级研究学院）；University of Liverpool（利物浦大学）
A low cost, stable, programmable, unipolar current source is described. The circuit is designed in view of a modular arrangement, suitable for applications where several DC sources must be controlled at once. A hybrid switching/linear design helps in improving the stability and in reducing the power dissipation and cross-talking. Multiple units can be supplied by a single DC power supply, while allowing for a variety of maximal current values and compliance voltages at the outputs. The circuit is analogically controlled by an unipolar voltage, enabling current programmability and control throu…
The same charge sensitive preamplifier and discriminator circuit with different isolation strategies has been tested to compare the isolation of both analog and digital circuits from the substrate of a 65nm bulk CMOS process to the isolation of only digital circuits, tying analog ground locally to the substrate. This study will show that the circuit with analog on the substrate and digital in deep N-well has better noise isolation between analog and digital.
This paper presents the experimental results of $17~MeV$ proton irradiation on a $60~GHz$ low power, half-duplex transceiver (TRX) chip implemented in $65~nm$ CMOS technology. It supports short range point-to-point data rate up to $6~Gbps$ by employing on-off keying (OOK). To investigate the irradiation hardness for high energy physics applications, two TRX chips were irradiated with total ionizing doses (TID) of $74~kGy$ and $42~kGy$ and fluence of $1.4~\times$10$^{14}~ N_{eq}/cm^2$ and $0.8~\times$10$^{14}~N_{eq}/cm^2$ for RX and TX modes, respectively. The chips were characterized by pre- a…
We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 degrees celsius shows negligible degradation over 16 days.
ITACA revisited: Ion Tracking Apparatus with CMOS ASICs
Donostia International Physics Center（多诺西亚国际物理中心）；Ben-Gurion University of the Negev（内盖夫本-古里安大学）；Instituto de Física Corpuscular (IFIC, CSIC-UV)（粒子物理研究所（IFIC，CSIC-UV））
