The existing ATLAS Tracker will be at its functional limit for particle fluences of 10^15 neq/cm^2 (LHC). Thus for the upgrades at smaller radii like in the case of the planned Insertable B-Layer (IBL) and for increased LHC luminosities (super LHC) the development of new structures and materials which can cope with the resulting particle fluences is needed. N-in-p silicon devices are a promising candidate for tracking detectors to achieve these goals, since they are radiation hard, cost efficient and are not type inverted after irradiation. A n-in-p pixel production based on a MPP/HLL design and performed by CiS (Erfurt, Germany) on 300 μm thick Float-Zone material is characterised and the electrical properties of sensors and single chip modules (SCM) are presented, including noise, charge collection efficiencies, and measurements with MIPs as well as an 241Am source. The SCMs are built with sensors connected to the current the ATLAS read-out chip FE-I3. The characterisation has been performed with the ATLAS pixel read-out systems, before and after irradiation with 24 GeV/c protons. In addition preliminary testbeam results for the tracking efficiency and charge collection, obtained with a SCM, are discussed.
To extend the physics reach of the LHC, accelerator upgrades are planned which will increase the integrated luminosity to beyond 3000 fb^-1 and the pile-up per bunch-crossing by a factor 5 to 10. To cope with the increased occupancy and radiation damage, the ATLAS experiment plans to introduce an all-silicon inner tracker with the HL-LHC upgrade. To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Upgrade Planar Pixel Sensor R&D Project (PPS) was established comprising 19 institutes and more than 80 scientists. Main areas of re…
The upgrade of the ATLAS muon spectrometer for high-luminosity LHC requires new trigger and readout electronics for the various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the ATLAS Monitored Drift Tube (MDT) detector. The chip was fabricated in a GlobalFoundries 130 nm CMOS technology. Studies indicate that its timing and power consumption characteristics meet the design specifications, with a timing bin variation of 40 ps for all 48 channels with a power consumption of about 6.5 mW per channel.
In view of the LHC upgrade phases towards HL-LHC the ATLAS experiment plans to upgrade the Inner Detector with an all silicon system. The n-in-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness, that allow for enlarging the area instrumented with pixel detectors. We present the characterization and performance of novel n-in-p planar pixel sensors produced by CiS (Germany) connected by bump bonding to the ATLAS readout chip FE-I3. These results are obtained before and after irradiation up to a fluence of 10^16 1-MeV n_eq/c…
The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a deplet…
With the LHC collecting data at 7 TeV, plans are already advancing for a series of upgrades leading eventually to about five times the LHC design luminosity some 10 years from now in the High Luminosity LHC (HL-LHC) project. The upgrades for ATLAS detector will be staged in preparation for HL-LHC. The first upgrade for the Pixel Detector will be the construction of a new pixel layer, which will be installed during the first shutdown of the LHC machine foreseen in 2013-14. The new detector, called the Insertable B-Layer (IBL) will be installed between the existing Pixel Detector and a new, smal…
The LHC accelerator complex will be upgraded between 2020-2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study no…
The Trigger Data Serializer (TDS) is a custom ASIC designed for the upgrade of the innermost station of the endcap ATLAS Muon Spectrometer. It is a mixed-signal chip with two working modes that can handle up to 128 detector channels. A total of 6,000 TDS ASICs have been produced for detector operation. This paper discusses a custom automatic test platform we developed to provide quality control of the TDS ASICs. We introduce the design, test procedures, and results obtained from this TDS testing platform.
A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to upgrade the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system is being developed for the LTDB and the major functions of the system have been evaluated. The design and evaluation of the clock and control system are presented in this paper.
The upgrade to the High Luminosity Large Hadron Collider will pose unprecedented challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors. This article presents studies with a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer. The device under test is structured in smaller pixels than those of the attached read-out chip with information on t…
We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this pape…
In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-um Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.
Two optical data link data transmission Application Specific Integrated Circuits (ASICs), the baseline and its backup, have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I trigger upgrade. The latency of each ASIC and that of its corresponding receiver implemented in a back-end Field-Programmable Gate Array (FPGA) are critical specifications. In this paper, we present the latency measurements and simulation of two ASICs. The measurement results indicate that both ASICs achieve their design goals and meet the latency specifications. The consistency between the simulation and …
In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R&D project by the ATLAS LPNHE Paris …
BDAQ53 is a readout system and verification framework for hybrid pixel detector readout chips of the RD53 family. These chips are designed for the upgrade of the inner tracking detectors of the ATLAS and CMS experiments. BDAQ53 is used in applications where versatility and rapid customization are required, such as in laboratory testing environments, test beam campaigns, and permanent setups for quality control measurements. It consists of custom and commercial hardware, a Python-based software framework, and FPGA firmware. BDAQ53 is developed as open source software with both software and firm…
The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which w…
The Robust Alignment algorithm for the ATLAS silicon detectors is presented. It is an iterative method based on centering residual and overlap residual distributions. Tests on simulated and real data are discussed.
The ATLAS experiment will replace the present Small Wheel (SW) detector with a New Small Wheel detector (NSW) aiming to improve the performance of muon triggering and precision tracking in the endcap region at the High-Luminosity LHC. Small-strip Thin Gap Chamber (sTGC) is one of the two new detector technologies used in this upgrade. A few custom-designed ASICs are needed for the sTGC detector. We designed an sTGC ASIC interface board to test ASIC-to-ASIC communication and validate the functionality of the entire system. A test platform with the final readout system is set up and the whole sT…
We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrica…
A serializer ASIC and a VCSEL driver ASIC are needed for the front-end optical data transmission in the ATLAS liquid argon calorimeter readout phase-I upgrade. The baseline ASICs are the serializer LOCx2 and the VCSEL driver LOCld, designed in a 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and consumed 843 mW and 320 mW, respectively. Based on a 130-nm CMOS technology, we design two pin-to-pin-compatible backup ASICs, LOCx2-130 and LOCld-130. Their power consumptions are much lower then of their counterparts, whereas other performance, such as the latency, data rate, and radiation toleran…
A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board. The board has 22 simplex optical links to transmit detector data, which are emulated in FPGAs and injected through 6 FMC connectors, to the off-detector electronics. The board implements 2 duplex optical links for clocks, control, and monitoring with redundant design to improve the system reliability. Data transmission and all redundant designs have been ver…
New front-end electronics including ASICs and FPGA boards are under development for the ATLAS Monitored Drift Tube (MDT) detector to handle the large data rates and harsh environment expected at high-luminosity LHC runs. A mobile Data Acquisition (miniDAQ) system is designed to perform integration tests of these front-end electronics. In addition, it will be used for surface commissioning of 96 small-radius MDT (sMDT) chambers and for integration and commissioning of new front-end electronics on the present ATLAS MDT chambers. Details of the miniDAQ hardware and firmware are described in this …
We present the results of the characterization of pixel modules composed of 75 um thick n-in-p sensors and ATLAS FE-I3 chips, interconnected with the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is explored as an alternative to the bump-bonding process. These modules have been designed to demonstrate the feasibility of a very compact detector to be employed in the future ATLAS pixel upgrades, making use of vertical integration technologies. This module concept also envisages Inter-Chip-Vias (ICV) to extract the signals from the backside of the c…
This paper presents a readout system designed for testing the prototype of Small-Strip Thin Gap Chamber (sTGC), which is one of the main detector technologies used for ATLAS New-Small-Wheel Upgrade. This readout system aims at testing one full-size sTGC quadruplet with cosmic muon triggers.
The ATLAS experiment pixel detector upgrade plans are focused on development of new technology, including the FE-I4 readout integrated circuit. The first upgrade project to make use of this new technology is an "Insertable B-Layer" (IBL) pixel detector to be installed on a replacement beam pipe in 2013. The IBL will fit inside and not alter the existing ATLAS pixel detector. However, the possibility is being studied to replace the pixel whole detector in 2018 with a lower mass, higher performance instrument based on the FE-I4 chip and new mechanical structures.
We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been implemented for the configuration and flow control logic. The total power consumption is increased by less than 10 mW while achieving the same time resolution and channel uniformity. A mini-DAQ system has been built to verify the front-end electronics chain with the new prototype together with other ASICs and boards in triggered mode. Cosmic ray tests with a small-…
The ATLAS detector has to undergo significant updates at the end of the current decade, in order to withstand the increased occupancy and radiation damage that will be produced by the high-luminosity upgrade of the Large Hadron Collider. In this presentation we give an overview of the recent accomplishments of the R&D activity on the planar pixel sensors for the ATLAS Inner Detector upgrade.
The LHC is expected to reach luminosities up to 3000fb-1 and the innermost layer of the ATLAS upgrade plans to cope with higher occupancy and to decrease the pixel size. 3D-Si sensors are a good candidate for the innermost layer of the ATLAS pixel upgrade since they exhibit good performance under high fluences and the new designs will have smaller pixel size to fulfill the electronics expectations. This paper reports TCAD simulations of the 3D-Si sensors designed at IMB-CNM with non passing-through columns that are being fabricated for the next innermost layer of the ATLAS pixel upgrade, shows…
This work presents a new silicon vertical JFET (V-JFET) device, based on the trenched 3D-detector technology developed at IMB-CNM, to be used as switches for the High-Voltage powering scheme of the ATLAS upgrade Inner Tracker. The optimization of the device characteristics is performed by 2D and 3D TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific requirements of the system. In addition, a set of parameter values has been extracted from the simulated curves to implement a SPICE model of the proposed V-JFET tran…
We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ~ 3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. The approach is adaptable…
We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size…
Following the Higgs particle discovery, the Large Hadron Collider complex will be upgraded in several phases allowing the luminosity to increase to $7 \times 10^{34}cm^{-2}s^{-1}$. In order to adapt the ATLAS detector to the higher luminosity environment after the upgrade, part of the ATLAS muon end-cap system, the Small Wheel, will be replaced by the New Small Wheel. The New Small Wheel includes two kinds of detectors: small-strip Thin Gap Chambers and Micromegas. Shandong University, part of the ATLAS collaboration, participates in the construction of the ATLAS New Small Wheel by developing,…
3D silicon sensors, where plasma micro-machining is used to etch deep narrow apertures in the silicon substrate to form electrodes of PIN junctions, represent possible solutions for inner pixel layers of the tracking detectors in high energy physics experiments. This type of sensors has been developed for the Insertable B-Layer (IBL), an additional pixel layer that has been installed in ATLAS during the present shutdown of the LHC collider at CERN. It is presented here the experience in designing, testing and qualifying sensors and detector modules that have been used to equip part of the IBL.…
Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. Depleted fully monolithic CMOS pixels with fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototy…
The innermost station of the present ATLAS forward muon detector needs to be upgraded for the super-LHC. We present a proposal to replace it with a sandwiched detector composed of several layers of small-radius Monitored Drift Tube chambers (sMDT) for precision tracking measurement and two stations of multi-gap Resistive Plate Chambers (mRPC) for triggering purpose. We describe the layout of the upgraded detector and the trigger strategy. Several modifications to the RPCs used in the ATLAS barrel region are needed to satisfy the super-LHC requirements. Various studies with the proposed mRPC ti…
The Large Hadron Collider (LHC) has been successfully delivering proton-proton collision data at the unprecedented center of mass energy of 13 TeV. An upgrade is planned to increase the instantaneous luminosity delivered by the LHC in what is called the HL-LHC, aiming to deliver a total of up 3000 fb$^{-1}$ to 4000 fb$^{-1}$ of data per experiment. To cope with the expected data-taking conditions ATLAS is planning upgrades of the detector. Six Technical Design Reports (TDR) were produced by the ATLAS Collaboration. In these TDRs the physics motivation and benefits of such upgrades are discusse…
We present the procedures and results of the quality control tests for the front-end optical link components in the ATLAS Liquid Argon Calorimeter Phase-1 upgrade. The components include a Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld, custom optical transmitter/transceiver modules MTx/MTRx, and a transmitter ASIC LOCx2. LOCld, MTx, and LOCx2 each contain two channels with the same structure, while MTRx has a transmitter channel and a receiver channel. Each channel is tested at 5.12 Gbps. A total of 5341 LOCld chips, 3275 MTx modules, 797 MTRx modules, and 3198 LOCx2 chips a…
The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is presented. The design consists of two pipeline A/D channels each with four Multiplying Digital-to-Analog Converters followed by 8-bit Successive-Approximation-Register analog-to-digital converters. The custom design, fabricated in a commercial 130 nm CMOS process, shows a performance of 67.9 dB SNDR at 10 MHz for a single channel at 40 MS/s, with a latency of 87.5 ns (to f…
After the successful LHC operation at the center-of-mass energies of 7 and 8 TeV in 2010-2012, plans are actively advancing for a series of upgrades of the accelerator, culminating roughly ten years from now in the high-luminosity LHC (HL-LHC) project, delivering of the order of five times the LHC nominal instantaneous luminosity along with luminosity leveling. The final goal is to extend the dataset from about few hundred fb$^{-1}$ to 3000 fb$^{-1}$ by around 2035 for ATLAS and CMS. In parallel, the experiments need to be kept lockstep with the accelerator to accommodate running beyond the no…
The small-strip Thin Gap Chamber (sTGC) will be used for both triggering and precision tracking purposes in the upgrade of the ATLAS forward muon spectrometer. Both sTGC pad and strip detectors are readout by a Trigger Data Serializer (TDS) ASIC in the trigger path. This ASIC has two operation modes to prepare trigger data from pad and strip detectors respectively. The pad mode (pad-TDS) collects the firing status for up to 104 pads from one detector layer and transmits the data at 4.8 Gbps to the pad trigger extractor every 25 ns. The pad trigger extractor collects pad-TDS data from eight det…
This paper presents several component prototypes towards a low-latency, small-form-factor optical link designed for the ATLAS Liquid Argon Calorimeter Phase-I trigger upgrade. A prototype of the custom-made dual-channel optical transmitter module, the Miniature optical Transmitter (MTx), with separate transmitter optical sub-assemblies (TOSAs) has been demonstrated at data rates up to 8 Gbps per channel. A Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC has been developed and is used in the current MTx prototypes. A serializer ASIC prototype, operating at up to 8 Gbps per channel, h…
Calibration of the discriminator threshold of the Amplifier-Shaper-Discriminator Chip for the Upgrade of the ATLAS Muon Drift-Tube Chambers for the High-Luminosity LHC
This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150\,nm CMOS process. DMAPS exploit high voltage and/or high resistivity inclusion of modern CMOS technologies to achieve substantial depletion in the sensing volume. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade in 2025 for the High Luminosity Large Hadron Collider (HL-LHC). This type of devices has a lower production cost and lower materia…
The FEB(front end board) configuration test board is developed aiming at meeting the requirement of testing the new generation ASIC(application-specific integrated circuit) chips and its configuration system for ATLAS NSW(New Small Wheel) upgrade, In this paper, some functions are developed in terms of the configurations of the key chips on the FEB, VMM3 and TDS2 using GBT-SCA. Additionally, a flexible communication protocol is designed, verifying the whole data link. It provides technical reference for prototype FEB key chip configuration and data readout, as well as the final system configur…
Micromegas is one of the detector technologies (along with the small Thin Gap Chambers) that has been chosen for precision tracking and triggering purposes of the ATLAS muon forward detectors in the view of LHC luminosity increase. To fulfill the requirements of such upgrade, several prototype micromegas detectors were tested in recent test beam campaigns with high energy hadron beams at CERN. Performance studies and results on spatial resolution for perpendicular and inclined tracks, efficiency, as well detector performance and comparison to simulation in a magnetic field are presented. Moreo…
With the LHC successfully collecting data at 7 TeV, plans are actively advancing for a series of upgrades leading eventually to about five times the LHC design-luminosity some 10-years from now in the High-Luminosity LHC (HL-LHC) project. Coping with the high instantaneous and integrated luminosity will require many changes to the ATLAS detector. The designs are developing rapidly for an all-new inner-tracker, significant changes in the calorimeter and muon systems, as well as improved triggers. This article summarizes the environment expected at the HL-LHC and the status of various improvemen…
We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize them, retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data a…
The instantaneous luminosity of the Large Hadron Collider at CERN will be increased by up to a factor of five to seven with respect to the design value. To maintain an excellent detection and background rejection capability in the forward region of the ATLAS detector, part of the muon detection system will be upgraded during LHC shutdown periods with the replacement of part of the present first station in the forward regions with the so-called New Small Wheels (NSWs). The NSWs will have a diameter of approximately 10 m and will be made of two detector technologies: Micromegas and small-strip T…
Small-diameter Muon Drift Tube (sMDT) chambers have been developed for the ATLAS muon detector upgrade. They possess an improved rate capability and a more compact design with respect to the existing chambers, which allows to equip detector regions uninstrument at present. The chamber assembly methods have been optimized for mass production, while the sense wire positioning accuracy is improved to below ten microns. The chambers will be ready for installation in the winter shutdown 2016/17 of the Large Hadron Collider. The design and construction of the new sMDT chambers for ATLAS will be disc…
After the first successful LHC run in 2010-2012, plans are actively advancing for a series of upgrades leading eventually to about above times the design-luminosity in about ten years. The larger luminosity will allow to perform precise measurements of the just discovered Higgs boson and to continue searching for new physics beyond the Standard Model. Coping with the high instantaneous and integrated luminosity will be a great challenge for the ATLAS detector and will require changes in most of the subsystems, specially those at low radii and large pseudorapidity, as well as in its trigger arc…
We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jit…
A radiation-hard quad-channel 12-bit 40 MSPS pipeline analog-to-digital converter (ADC) has been designed for the trigger readout electronics Phase-I upgrade of the ATLAS Liquid Argon calorimeter, at the CERN Large Hadron Collider. The final version of the custom design, fabricated in a commercial 130 nm CMOS process, is presented and found to meet the system requirements for analog performance and radiation tolerance. The procedure for quality control of 17200 ADCs is described and the results are presented.
The ATLAS Planar Pixel Sensor R&D Project is a collaboration of 17 institutes and more than 80 scientists. Their goal is to explore the operation of planar pixel sensors for the tracker upgrade at the High Luminosity-Large Hadron Collider (HL-LHC). This work will give a summary of the achievements on radiation studies with n-in-n and n-in-p pixel sensors, bump-bonded to ATLAS FE-I3 and FE-I4 readout chips. The summary includes results from tests with radioactive sources and tracking efficiencies extracted from test beam measurements. Analysis results of ${2\cdot10^{16}} \text{n}_{\text{eq}}\te…
For Run 3 (from 2021), the LHC will undergo a significant increase in instantaneous luminosity to 1.5 times its current value which will lead to larger collected statistics and an enhanced sensitivity to new physics. The Phase-1 upgrade of the ATLAS Level-1 endcap muon trigger is essential to keep the physics acceptance at Run 3. A new trigger logic to take coincidence with detectors inside and outside the magnetic field is described and is shown to reduce the trigger rate to lower than the required level in Run 3. A new trigger board, NSL, to integrate all the information from various detecto…
In order to meet the requirements of the High Luminosity LHC (HL-LHC), it will be necessary to replace the current tracker of the ATLAS experiment. Therefore, a new all-silicon tracking detector is being developed, the so-called Inner Tracker (ITk). The use of quad chip modules is intended in its pixel region. These modules consist of a silicon sensor that forms a unit along with four read-out chips. The current ATLAS pixel detector consists of planar n-in-n silicon pixel sensors. Similar sensors and four FE-I4 read-out chips were assembled to first prototypes of planar n-in-n quad modules. Th…
A completely New Small Wheel (NSW) will be constructed for ATLAS Phase-1 upgrade. Small-Strip Thin-Gap-Chamber (sTGC) will devote to the trigger function of NSW. A full-size sTGC quadruplet consists of 4 layers, and will need 4 pad Front-End-Boards and 4 strip Front-End-Boards for sTGC signals readout. The 8 boards should be readout simultaneously at a time. This paper presents the study of multi-layer sTGC test system, a FEB Driver Card (FEBDC) is designed for pFEB and sFEB boards handling. The design and test of FEBDC are described in details.
