考虑互连电阻的闭环模拟矩阵计算电路建模
Modeling Closed-loop Analog Matrix Computing Circuits with Interconnect Resistance
AI总结：
针对互连电阻降低AMC电路精度和可扩展性、传统SPICE仿真低效的问题，提出基于雅可比矩阵稀疏性的快速求解算法，实现多数量级加速，还开发偏置补偿策略大幅减少误差并揭示最优偏置缩放行为。
摘要：
基于阻变随机存取存储器（RRAM）的模拟矩阵计算（AMC）电路在加速矩阵运算方面展现出强大潜力。然而，随着矩阵规模增大，互连电阻会显著降低计算精度并限制电路可扩展性，因此建模和评估这些影响对制定有效缓解策略至关重要。传统的SPICE（集成电路仿真程序）模拟器依赖改进节点分析，由于节点和反馈连接的二次增长，对大规模AMC电路的仿真速度慢到难以接受。本研究针对矩阵求逆（INV）和特征向量计算（EGV）两种关键运算，对含互连电阻的AMC电路进行建模，并为每种情况提出定制化快速求解算法。这些算法利用雅可比矩阵的稀疏性，实现快速且准确的求解。与SPICE相比，它们在保持高精度的同时实现了多个数量级的加速。我们进一步将该方法扩展到开环矩阵-向量乘法（MVM）电路，证明了类似的效率提升。最后，利用这些快速求解器，我们开发了一种基于偏置的补偿策略，使INV电路的互连诱导误差减少50%以上，EGV电路减少70%以上，还揭示了最优偏置随矩阵规模和互连电阻的缩放行为。
英文摘要：
Analog matrix computing (AMC) circuits based on resistive random-access memory (RRAM) have shown strong potential for accelerating matrix operations. However, as matrix size grows, interconnect resistance increasingly degrades computational accuracy and limits circuit scalability. Modeling and evaluating these effects are therefore critical for developing effective mitigation strategies. Traditional SPICE (Simulation Program with Integrated Circuit Emphasis) simulators, which rely on modified nodal analysis, become prohibitively slow for large-scale AMC circuits due to the quadratic growth of nodes and feedback connections. In this work, we model AMC circuits with interconnect resistance for two key operations-matrix inversion (INV) and eigenvector computation (EGV), and propose fast solving algorithms tailored for each case. The algorithms exploit the sparsity of the Jacobian matrix, enabling rapid and accurate solutions. Compared to SPICE, they achieve several orders of magnitude acceleration while maintaining high accuracy. We further extend the approach to open-loop matrix-vector multiplication (MVM) circuits, demonstrating similar efficiency gains. Finally, leveraging these fast solvers, we develop a bias-based compensation strategy that reduces interconnect-induced errors by over 50% for INV and 70% for EGV circuits. It also reveals the scaling behavior of the optimal bias with respect to matrix size and interconnect resistance.
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