一种适用于片上计算和通信的通用多层次性能指标
A Universal Multi-Hierarchy Figure-of-Merit for On-Chip Computing and Communications
摘要：
对提高计算效率和通信带宽的持续需求已经导致了具有超越传统电互连的潜力的新型互连技术的发展。在包括电子、光子、等离子体及其混合的多种互连技术的情况下，计数片上器件以捕获性能的简单方法是不够的。虽然已经做出了一些努力来更准确地捕捉性能演变，但它们最终偏离了观察到的开发速度。因此，需要一个整体品质因数（FOM）来充分比较这些最新的技术范式。在这里，我们介绍的能力，潜在的能量，数量，电阻（CLEAR）FOM来自设备和链路的性能标准的有源光电器件和无源元件一样。因此，CLEAR结合了通信延迟、能效、片上缩放和经济成本。我们表明，CLEAR准确地描述了计算机的发展，包括最近的机器。由于该FOM是自下而上导出的，因此我们展示了从设备级到网络和系统级的应用的显著适应性。将CLEAR应用于基准设备、链路和网络性能，以对抗基本的物理计算和通信限制，表明光子学即使在芯片尺寸的几分之一上也具有竞争力，从而为片上光学互连提供了理由。
英文摘要：
Continuing demands for increased compute efficiency and communication bandwidth have led to the development of novel interconnect technologies with the potential to outperform conventional electrical interconnects. With a plurality of interconnect technologies to include electronics, photonics, plasmonics, and hybrids thereof, the simple approach of counting on-chip devices to capture performance is insufficient. While some efforts have been made to capture the performance evolution more accurately, they eventually deviate from the observed development pace. Thus, a holistic figure of merit (FOM) is needed to adequately compare these recent technology paradigms. Here we introduce the Capability-to-Latency-Energy-Amount-Resistance (CLEAR) FOM derived from device and link performance criteria of both active optoelectronic devices and passive components alike. As such CLEAR incorporates communication delay, energy efficiency, on-chip scaling and economic cost. We show that CLEAR accurately describes compute development including most recent machines. Since this FOM is derived bottom-up, we demonstrate remarkable adaptability to applications ranging from device-level to network and system-level. Applying CLEAR to benchmark device, link, and network performance against fundamental physical compute and communication limits shows that photonics is competitive even for fractions of the die-size, thus making a case for on-chip optical interconnects.
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