A time-domain analog-weighted-sum calculation model based on a pulse-width modulation (PWM) approach is proposed. The proposed calculation model can be applied to any types of network structure including multi-layer feedforward networks. We also propose very large-scale integrated (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits used in computing-in-memory circuits, our time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can be operated with extremely low power consumption. However, they have to use very high-resistance devices, on the order of giga-ohms. We designed a CMOS VLSI chip to verify weighted-sum operation based on the proposed model with binary weights, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors unlike the ordinary computing-in-memory circuits. The chip was designed and fabricated using a 250-nm fabrication technology. Measurement results showed that energy efficiency for the weighted-sum calculation was 300~TOPS/W (Tera-Operations Per Second per Watt), which is more than one order of magnitude higher than that in state-of-the-art digital AI processors, even though the minimum width of interconnection used in this chip was several times larger than that in such digital processors. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000~TOPS/W will be possible. For practical applications, development of emerging analog memory devices such as ferroelectric-gate field effect transistors (FeFETs) is necessary.
Parameter Optimization and Learning in a Spiking Neural Network for UAV Obstacle Avoidance targeting Neuromorphic Processors
Lobula Giant Movement Detector（LGMD）是蝗虫的一个识别神经元，它可以检测到隐约可见的物体并触发昆虫的逃跑反应。理解导致这些快速和鲁棒响应的神经原理和网络结构可以促进机器人应用的有效避障策略的设计。在这里，我们提出了一个神经形态脉冲神经网络模型的LGMD驱动的神经形态动态视觉传感器（DVS），它结合了尖峰频率适应和突触可塑性机制，并可以映射到现有的神经形态处理器芯片的输出。然而，由于该模型的参数范围很广，并且用于实现该模型的混合信号模数电路受到变化性和噪声的影响，因此有必要优化参数以产生鲁棒且可靠的响应。在这里，我们建议使用差分进化（DE）和贝叶斯优化（BO）技术来优化参数空间，并研究使用自适应差分进化（SADE），以改善困难的DE技术找到合适的输入参数。我们量化的性能提出的方法与应用于模型的不同的优化器的全面比较，并证明了使用从安装在无人机上的DVS传感器的记录所提出的方法的有效性。
