全模拟存内计算架构中的互连寄生效应与划分方法
Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures
AI总结：
针对全模拟存内计算架构中互连寄生参数影响DNN精度的问题，提出阵列划分缓解机制，在MNIST任务上实现接近数字CPU实现的精度，代价是功耗有所增加。
摘要：
全模拟存内计算（IMC）架构可在同一存储阵列内实现矩阵-向量乘法与非线性向量运算，由于省去了高能耗的信号转换单元，相比传统IMC系统展现出可观的性能优势。然而，在整个深度神经网络（DNN）的计算过程中始终保持模拟域运算，会导致系统对互连寄生参数存在潜在敏感性。因此，本文研究了导线寄生电阻和电容对部署在全模拟IMC架构上的DNN模型精度的影响。此外，我们提出了一种划分机制，通过将大型阵列拆分为多个分区，在保持模拟域计算的同时缓解寄生效应的影响。针对部署在全模拟IMC电路上的400×120×84×10 DNN模型的SPICE电路仿真结果表明，在MNIST分类任务中，当DNN的第一层、第二层、第三层分别采用16、8、8个水平分区以及8、8、1个垂直分区时，可实现94.84%的精度，这一结果与CPU上数字实现达到的约97%的精度相当。研究表明，精度提升的代价是功耗升高，这是由于处理划分需要额外的电路。
英文摘要：
Fully-analog in-memory computing (IMC) architectures that implement both matrix-vector multiplication and non-linear vector operations within the same memory array have shown promising performance benefits over conventional IMC systems due to the removal of energy-hungry signal conversion units. However, maintaining the computation in the analog domain for the entire deep neural network (DNN) comes with potential sensitivity to interconnect parasitics. Thus, in this paper, we investigate the effect of wire parasitic resistance and capacitance on the accuracy of DNN models deployed on fully-analog IMC architectures. Moreover, we propose a partitioning mechanism to alleviate the impact of the parasitic while keeping the computation in the analog domain through dividing large arrays into multiple partitions. The SPICE circuit simulation results for a 400 X 120 X 84 X 10 DNN model deployed on a fully-analog IMC circuit show that a 94.84% accuracy could be achieved for MNIST classification application with 16, 8, and 8 horizontal partitions, as well as 8, 8, and 1 vertical partitions for first, second, and third layers of the DNN, respectively, which is comparable to the ~97% accuracy realized by digital implementation on CPU. It is shown that accuracy benefits are achieved at the cost of higher power consumption due to the extra circuitry required for handling partitioning.
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