ALPHA-PIM：高性能量子图应用在真实处理-内存系统中的线性代数处理分析
ALPHA-PIM: Analysis of Linear Algebraic Processing for High-Performance Graph Applications on a Real Processing-In-Memory System
AI总结：
本研究探讨了在真实PIM系统中优化图算法性能，通过数据分区策略和硬件改进提升计算效率。
摘要：
处理大规模图数据集计算密集且耗时。以处理器为中心的CPU和GPU架构，常用于图应用，由于低数据重用率导致处理器与内存单元之间大量的数据移动而产生瓶颈。因此，这些应用通常是内存受限的，由于过多的数据传输限制了性能和能效。处理-内存（PIM）通过将计算直接集成在内存中或附近来缓解数据移动瓶颈。尽管已有研究提出了针对图处理的定制PIM方案，但并未利用真实世界中的PIM系统。本研究旨在探索常见图算法在真实PIM系统中的能力和特性，以加速数据密集型图工作负载。为此，我们（1）在UPMEM的通用PIM架构上实现代表性图算法；（2）表征其性能并识别关键瓶颈；（3）将结果与CPU和GPU基准进行比较；（4）得出见解以指导未来的PIM硬件设计。我们的研究强调了在PIM核心之间选择最优的数据分区策略以最大化性能的重要性。此外，我们识别了当前PIM架构中的关键硬件限制，并强调了未来在计算、内存和通信子系统方面的改进需求。改进的关键机会包括增加指令级并行性、开发改进的DMA引擎以具备非阻塞能力，以及启用PIM核心之间的直接互连网络以减少数据传输开销。
英文摘要：
Processing large-scale graph datasets is computationally intensive and time-consuming. Processor-centric CPU and GPU architectures, commonly used for graph applications, often face bottlenecks caused by extensive data movement between the processor and memory units due to low data reuse. As a result, these applications are often memory-bound, limiting both performance and energy efficiency due to excessive data transfers. Processing-In-Memory (PIM) offers a promising approach to mitigate data movement bottlenecks by integrating computation directly within or near memory. Although several previous studies have introduced custom PIM proposals for graph processing, they do not leverage real-world PIM systems. This work aims to explore the capabilities and characteristics of common graph algorithms on a real-world PIM system to accelerate data-intensive graph workloads. To this end, we (1) implement representative graph algorithms on UPMEM's general-purpose PIM architecture; (2) characterize their performance and identify key bottlenecks; (3) compare results against CPU and GPU baselines; and (4) derive insights to guide future PIM hardware design. Our study underscores the importance of selecting optimal data partitioning strategies across PIM cores to maximize performance. Additionally, we identify critical hardware limitations in current PIM architectures and emphasize the need for future enhancements across computation, memory, and communication subsystems. Key opportunities for improvement include increasing instruction-level parallelism, developing improved DMA engines with non-blocking capabilities, and enabling direct interconnection networks among PIM cores to reduce data transfer overheads.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
