通过高层次综合评估大语言模型自动生成寄存器传输级逻辑的能力
Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis
AI总结：
本文提出LLM生成带注释C++代码再经高层次综合生成Verilog RTL的两阶段流水线，在VerilogEval上以0.86的pass@1显著优于直接生成Verilog的方法。
摘要：
大语言模型（LLMs）日益增长的普及度促使其在硬件设计与验证中的应用不断增加。此前的研究尝试评估LLMs通过生成高质量寄存器传输级（RTL）描述（尤其是Verilog）来自动化数字硬件设计的能力。然而，这些测试表明，与C、C++、Python等通用编程语言程序的自动生成相比，使用当前最先进的LLMs生成Verilog代码在功能正确性方面仍不足以具备实际可行性。基于这一关键认识，本文评估了一种用于自动化Verilog RTL生成的两阶段软件流水线的性能：首先由LLM自动生成适用于高层次综合（HLS）的带注释C++代码，随后通过HLS生成Verilog RTL。我们使用开源VerilogEval数据集、四种不同工业规模LLMs以及Vitis HLS工具，对所提方案的性能进行了基准测试。实验结果表明，我们的两步技术在平均功能正确率方面显著优于此前提出的由LLMs直接生成Verilog RTL的技术，在pass@1指标上达到0.86分。
英文摘要：
The ever-growing popularity of large language models (LLMs) has resulted in their increasing adoption for hardware design and verification. Prior research has attempted to assess the capability of LLMs to automate digital hardware design by producing superior-quality Register Transfer Logic (RTL) descriptions, particularly in Verilog. However, these tests have revealed that Verilog code production using LLMs at current state-of-the-art lack sufficient functional correctness to be practically viable, compared to automatic generation of programs in general-purpose programming languages such as C, C++, Python, etc. With this as the key insight, in this paper we assess the performance of a two-stage software pipeline for automated Verilog RTL generation: LLM based automatic generation of annotated C++ code suitable for high-level synthesis (HLS), followed by HLS to generate Verilog RTL. We have benchmarked the performance of our proposed scheme using the open-source VerilogEval dataset, for four different industry-scale LLMs, and the Vitis HLS tool. Our experimental results demonstrate that our two-step technique substantially outperforms previous proposed techniques of direct Verilog RTL generation by LLMs in terms of average functional correctness rates, reaching score of 0.86 in pass@1 metric.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
