用于可重配置逻辑设计的分布式存储器局部配置技术
A distributed memory, local configuration technique for re-configurable logic designs
摘要：
集成电路中存储器的使用和位置对其性能起着关键作用。内存需要较大的物理区域，访问时间限制了整体系统性能，并且连接可能导致大量扇出。现代FPGA系统和ASIC包含一个存储器区域，用于根据主机设置的一系列命令设置设备的操作。实现这些设置寄存器需要一定程度的谨慎，否则所得到的实现可能导致大量消耗宝贵资源的大型扇出网络，从而使时序关键路径的放置复杂化。本文提出了一种架构，用于实现和编程这些设置寄存器在一个分布式的方法在FPGA和所提出的架构如何工作在时钟域交叉和动态部分重新配置应用。该设计相比，一个“全球”设置寄存器架构。我们实现的架构，使用英特尔FPGA的Quartus Prime软件针对英特尔FPGA旋风V。它表明，分布式存储器架构具有较小的资源成本（小至25%的ALM和20%的寄存器）相比，全球存储器架构。
英文摘要：
The use and location of memory in integrated circuits plays a key factor in their performance. Memory requires large physical area, access times limit overall system performance and connectivity can result in large fan-out. Modern FPGA systems and ASICs contain an area of memory used to set the operation of the device from a series of commands set by a host. Implementing these settings registers requires a level of care otherwise the resulting implementation can result in a number of large fan-out nets that consume valuable resources complicating the placement of timing critical pathways. This paper presents an architecture for implementing and programming these settings registers in a distributed method across an FPGA and how the presented architecture works in both clock-domain crossing and dynamic partial re-configuration applications. The design is compared to that of a `global' settings register architecture. We implement the architectures using Intel FPGAs Quartus Prime software targeting an Intel FPGA Cyclone V. It is shown that the distributed memory architecture has a smaller resource cost (as small as 25% of the ALMs and 20% of the registers) compared to the global memory architectures.
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