65 nm CMOS微处理器实现的可配置和位可扩展加速器用于可编程存内计算
A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing
摘要：
本文介绍了一种可编程的内存计算处理器，在65纳米CMOS工艺证明。对于以数据为中心的工作负载，例如深度神经网络，在使用当今的计算架构实现时，数据移动通常占主导地位。这激发了空间架构的发展，其中数据存储和计算硬件的布置是分布式的，并与计算数据流显式对齐，最明显的是对于矩阵向量乘法。存内计算是一种空间架构，其中处理元件对应于密集位单元，提供本地存储和计算，通常采用模拟操作。虽然这提高了高能效和高吞吐量的潜力，但模拟操作的鲁棒性、规模和可编程性受到极大限制。本文介绍了一个590 kb的内存计算加速器集成在一个可编程处理器架构，利用最近的方法，电荷域存内计算。该架构采用与嵌入式CPU紧密耦合的方法，通过加速器接口实现标准处理器内存空间的集成。此外，近存储器计算数据路径通过位并行/位串行（BP/BS）方案既能够在本地实现各种计算，以解决跨应用所需的操作，又能够实现矩阵/输入向量元素的位精度可扩展性。芯片测量显示，在VDD为1.2/0.85V时，能量效率为152/297 1b-TOPS/W，吞吐量为4.7/1.9 1b-TOPS（与矩阵/输入向量元素精度线性缩放）。具有1-b/4-b权重和激活的CIFAR-10分类的神经网络演示在176/23 fps下消耗5.3/105.2 $μ$ J/图像，其准确度在数字/软件实现的水平（89.3/92.4 $\%$准确度）。
英文摘要：
This paper presents a programmable in-memory-computing processor, demonstrated in a 65nm CMOS technology. For data-centric workloads, such as deep neural networks, data movement often dominates when implemented with today's computing architectures. This has motivated spatial architectures, where the arrangement of data-storage and compute hardware is distributed and explicitly aligned to the computation dataflow, most notably for matrix-vector multiplication. In-memory computing is a spatial architecture where processing elements correspond to dense bit cells, providing local storage and compute, typically employing analog operation. Though this raises the potential for high energy efficiency and throughput, analog operation has significantly limited robustness, scale, and programmability. This paper describes a 590kb in-memory-computing accelerator integrated in a programmable processor architecture, by exploiting recent approaches to charge-domain in-memory computing. The architecture takes the approach of tight coupling with an embedded CPU, through accelerator interfaces enabling integration in the standard processor memory space. Additionally, a near-memory-computing datapath both enables diverse computations locally, to address operations required across applications, and enables bit-precision scalability for matrix/input-vector elements, through a bit-parallel/bit-serial (BP/BS) scheme. Chip measurements show an energy efficiency of 152/297 1b-TOPS/W and throughput of 4.7/1.9 1b-TOPS (scaling linearly with the matrix/input-vector element precisions) at VDD of 1.2/0.85V. Neural network demonstrations with 1-b/4-b weights and activations for CIFAR-10 classification consume 5.3/105.2 $μ$J/image at 176/23 fps, with accuracy at the level of digital/software implementation (89.3/92.4 $\%$ accuracy).
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