安全RISC-V微处理器的设计与实现
Design and Implementation of a Secure RISC-V Microprocessor
摘要：
密钥可以从未受保护设备的功耗或电磁辐射中提取。传统的反措施保护范围有限，并对如何操纵敏感数据施加了一些限制。我们展示了一个位串行RISC-V微处理器实现没有明文数据。所有值都使用布尔掩码进行保护。软件可以在几乎没有反措施的情况下运行，从而减少代码大小和性能开销。与以前的文献不同，我们的方法是完全自动化的，可以应用于任意大小或复杂性的设计。我们还提供了其他关键组件，如时钟随机发生器，内存保护和随机数发生器的细节。该微处理器采用65 nm CMOS工艺实现。它的实现使用NIST测试以及侧信道攻击进行了评估。我们的RNG生成的随机数通过了所有NIST测试。对基线实现的侧通道分析仅使用375个跟踪提取AES密钥，而我们的安全微处理器能够承受使用20 M跟踪的攻击。
英文摘要：
Secret keys can be extracted from the power consumption or electromagnetic emanations of unprotected devices. Traditional counter-measures have limited scope of protection, and impose several restrictions on how sensitive data must be manipulated. We demonstrate a bit-serial RISC-V microprocessor implementation with no plain-text data. All values are protected using Boolean masking. Software can run with little to no counter-measures, reducing code size and performance overheads. Unlike previous literature, our methodology is fully automated and can be applied to designs of arbitrary size or complexity. We also provide details on other key components such as clock randomizer, memory protection, and random number generator. The microprocessor was implemented in 65 nm CMOS technology. Its implementation was evaluated using NIST tests as well as side channel attacks. Random numbers generated with our RNG pass on all NIST tests. Side-channel analysis on the baseline implementation extracted the AES key using only 375 traces, while our secure microprocessor was able to withstand attacks using 20 M traces.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
