arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2009.05262cs.CR
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HECTOR-V:一种用于安全RISC-V执行环境的异构CPU体系结构

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment

Pascal Nasahl, Robert Schilling, Mario Werner, Stefan Mangard

摘要:

为了确保应用程序的安全和可信执行,供应商经常将可信执行环境嵌入到他们的系统中。在这里,应用程序受到保护,免受包括恶意操作系统在内的攻击。TEE通常通过将保护机制直接集成到处理器中或通过使用专用的外部安全元件来构建。然而,这两种方法都只覆盖了一个狭窄的威胁模型,导致有限的安全保证。应用处理器中的飞地通常在安全域和非安全域之间提供弱隔离,特别是在考虑侧信道攻击时。尽管安全元件确实提供了强隔离,但到应用处理器的缓慢通信接口暴露给对手并限制了用例。与所使用的实现方法无关,TEE通常缺乏与外部外围设备建立安全通信的可能性,并且在TEE内执行的大多数操作系统不提供最先进的防御策略,使得它们容易受到各种攻击。我们认为,在主应用程序处理器上实现的TEE是不安全的,特别是当考虑到侧信道攻击。我们演示了如何利用异构体系结构来实现安全的TEE设计。我们直接将处理器嵌入到我们的架构中,以提供安全域和非安全域之间的强隔离。TEE和REE的紧密耦合使HECTOR-V能够提供用于建立安全通信通道的机制。我们还介绍了RISC-V安全协处理器,这是一款为TEE量身定制的安全加固处理器。为了保护在TEE内部执行的应用程序,RVSCP提供控制流完整性,严格限制I/O访问某些执行状态,并直接在硬件中提供操作系统服务。

英文摘要:

To ensure secure and trustworthy execution of applications, vendors frequently embed trusted execution environments into their systems. Here, applications are protected from adversaries, including a malicious operating system. TEEs are usually built by integrating protection mechanisms directly into the processor or by using dedicated external secure elements. However, both of these approaches only cover a narrow threat model resulting in limited security guarantees. Enclaves in the application processor typically provide weak isolation between the secure and non-secure domain, especially when considering side-channel attacks. Although secure elements do provide strong isolation, the slow communication interface to the application processor is exposed to adversaries and restricts the use cases. Independently of the used implementation approach, TEEs often lack the possibility to establish secure communication to external peripherals, and most operating systems executed inside TEEs do not provide state-of-the-art defense strategies, making them vulnerable against various attacks. We argue that TEEs implemented on the main application processor are insecure, especially when considering side-channel attacks. We demonstrate how a heterogeneous architecture can be utilized to realize a secure TEE design. We directly embed a processor into our architecture to provide strong isolation between the secure and non-secure domain. The tight coupling of TEE and REE enables HECTOR-V to provide mechanisms for establishing secure communication channels. We further introduce RISC-V Secure Co-Processor, a security-hardened processor tailored for TEEs. To secure applications executed inside the TEE, RVSCP provides control-flow integrity, rigorously restricts I/O accesses to certain execution states, and provides operating system services directly in hardware.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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