混合关键性RISC-V系统级隔离：一个“世界”的现实检验
System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
AI总结：
本文研究了混合关键性RISC-V系统级隔离问题，通过实现和评估多种隔离原语，提出改进方案以提高安全性和效率。
摘要：
随着RISC-V的采用加速，汽车、物联网（IoT）和工业控制等领域的关注度不断上升。这些领域受到严格尺寸、重量、功率和成本（SWaP-C）约束，推动了异构系统级芯片（SoC）的发展，集成了通用CPU、紧密耦合的加速器和具有不同完整性级别的多样化I/O设备。尽管这种集成提高了成本效率和性能，但引入了根本的安全和安全挑战：在混合关键性环境中实施系统级隔离。虽然RISC-V国际提出了几种硬件隔离原语，包括RISC-V Worlds、IOPMP和SmMTT，但它们的互操作性、可扩展性和适用于实时系统的能力仍不够清楚。在本文中，我们从实际异构SoC设计的角度对这些原语进行了比较分析。我们实现了一个IOPMP、一个基于World的检查器和一个修改后的RISC-V World检查器，以解决基线规范的关键限制，并评估其在安全保证和功率-性能-面积（PPA）方面的权衡。我们的结果表明，基于World的检查器引入了固定的、配置无关的访问延迟，实现了比评估的替代方案更低的最坏情况延迟，同时系统规模可预测地扩展。在宏观层面，我们估计所提出修改将SoC面积减少了约5%。所有成果将作为开源发布，我们期望这些发现将直接促进RISC-V规范的演变和批准，以及未来RISC-V SoC的设计。
英文摘要：
As RISC-V adoption accelerates, domains such as automotive, the Internet of Things (IoT), and industrial control are attracting growing attention. These domains are subject to stringent Size, Weight, Power, and Cost (SWaP-C) constraints, which have driven a shift toward heterogeneous Systems-on-Chip (SoCs) integrating general-purpose CPUs, tightly coupled accelerators, and diverse I/O devices with different integrity levels. While such integration improves cost efficiency and performance, it introduces a fundamental safety and security challenge: enforcing system-level isolation in mixed-criticality environments. Although RISC-V International has proposed several hardware isolation primitives, including RISC-V Worlds, IOPMP, and SmMTT, their interoperability, scalability, and suitability for real-time systems remain insufficiently understood. In this paper, we present a comparative analysis of these primitives from the perspective of practical heterogeneous SoC designs. We implement an IOPMP, a World-based checker, and a modified RISC-V World checker that addresses key limitations of the baseline specification, and evaluate their trade-offs in terms of security guarantees and power-performance-area (PPA). Our results show that the World-based checker introduces a fixed, configuration-independent access latency, achieving lower worst-case delay than the evaluated alternatives while scaling predictably with system size. At the macro level, we estimate that the proposed modifications reduce SoC area by up to approximately 5% compared to a baseline design. All artifacts will be released as open source, and we expect these findings to directly contribute to the evolution and ratification of RISC-V specifications, as well as to the design of future RISC-V SoCs.
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