评估16nm FinFET中带实际功率时钟的正反馈绝热逻辑
Evaluating Positive Feedback Adiabatic Logic in 16nm FinFET with a Realistic Power-Clock
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中文总结 AI 辅助
本研究在16nm FinFET工艺下系统评估正反馈绝热逻辑（PFAL），通过标准单元和组合电路仿真，揭示非绝热损耗来源，并设计实际功率时钟，证明其在低功耗架构中的能量优势。
中文摘要 AI 辅助
绝热逻辑通过准可逆开关复用负载电容上存储的能量，从而比传统静态CMOS实现更低的能耗下限。然而，其在FinFET技术及多GHz时钟频率下的实用性尚未得到研究。本工作对在TSMC 16nm FinFET工艺中仿真的正反馈绝热逻辑（PFAL）进行了系统评估。实现了一组PFAL标准单元门，以及两个代表性组合电路——一个2×2乘法器和一个4位比较器——并使用能量-延迟积（EDP）和能量优势指标η = E_CMOS / E_PFAL与静态CMOS逻辑进行了比较。瞬态仿真揭示了三种非绝热损耗来源：两种特定于PMOS/NMOS锁存器，即阈值电压相关损耗和一种先前未报道的输出节点冗余充电，以及一种与PFAL逻辑树复杂度相关的损耗。低阈值Buffer/NOT单元在V_CLK = 0.6V和f_CLK = 7.94GHz时实现了最小EDP为1.23×10^-26 J·s，而PFAL在降低频率和提高电源电压下相比静态CMOS保持了高达约5倍的能量优势。设计了一个并行耦合正交压控振荡器作为实际的四相功率时钟发生器。在这种非理想电源下，Buffer/NOT能量在3GHz时保持在理想正弦情况下的2%以内。负载研究量化了由增加扇出引起的相移和幅度降低。总体而言，结果为16nm FinFET中的PFAL提供了面向设计的评估，并激励在未来低功耗系统架构中利用绝热逻辑。
英文摘要
Adiabatic logic reuses the energy stored on load capacitances through quasi-reversible switching, enabling a lower minimum energy consumption than conventional static CMOS. Yet its practicality in FinFET technologies and at multi-GHz clock rates has yet to be investigated. This work provides a systematic evaluation of Positive Feedback Adiabatic Logic (PFAL) simulated in the TSMC 16nm FinFET process. A set of PFAL standard-cell gates were realised, along with two representative combinational circuits - a 2$\times$2 multiplier and a 4-bit comparator - and compared against static CMOS logic using the energy--delay product (EDP) and the energy advantage metric $η= E_{\mathrm{CMOS}} / E_{\mathrm{PFAL}}$. Transient simulations reveal three sources of non-adiabatic loss: two specific to the PMOS/NMOS latch, threshold-voltage-related loss and a previously unreported redundant charging of the output node and one related to the complexity of PFAL logic trees. The low-threshold Buffer/NOT cell achieves a minimum EDP of $1.23\times10^{-26}$J$\cdot$s at $V_{\mathrm{CLK}} = 0.6$V and $f_{\mathrm{CLK}} = 7.94$GHz, while PFAL preserves an energy benefit over static CMOS of up to roughly $5\times$ at reduced frequencies and elevated supply voltages. A parallel-coupled quadrature voltage-controlled oscillator is designed as a realistic four-phase power-clock generator. With this non-ideal supply, the Buffer/NOT energy stays within $2\%$ of the ideal sinusoidal case at $3$GHz. A loading study quantifies the phase shift and amplitude reduction induced by increasing fan-out. Overall, the results provide a design-oriented evaluation of PFAL in 16nm FinFET and a motivation to exploit adiabatic logic for future low-power system architectures.
发表机构
- Eindhoven University of Technology（埃因霍温理工大学）
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