The memory system is a major performance determinant for server processors. Ever-growing core counts and datasets demand higher bandwidth and capacity as well as lower latency from the memory system. To keep up with growing demands, DDR--the dominant processor interface to memory over the past two decades--has offered higher bandwidth with every generation. However, because each parallel DDR interface requires a large number of on-chip pins, the processor's memory bandwidth is ultimately restrained by its pin-count, which is a scarce resource. With limited bandwidth, multiple memory requests typically contend for each memory channel, resulting in significant queuing delays that often overshadow DRAM's service time and degrade performance.
We present CoaXiaL, a server design that overcomes memory bandwidth limitations by replacing \textit{all} DDR interfaces to the processor with the more pin-efficient CXL interface. The widespread adoption and industrial momentum of CXL makes such a transition possible, offering $4\times$ higher bandwidth per pin compared to DDR at a modest latency overhead. We demonstrate that, for a broad range of workloads, CXL's latency premium is more than offset by its higher bandwidth. As CoaXiaL distributes memory requests across more channels, it drastically reduces queuing delays and thereby both the average value and variance of memory access latency. Our evaluation with a variety of workloads shows that CoaXiaL improves the performance of manycore throughput-oriented servers by $1.52\times$ on average and by up to $3\times$.
Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting
School of Electrical；Computer Engineering Georgia Institute of Technology Atlanta, Georgia, USA Email；School of Computer Science Georgia Institute of Technology Atlanta, Georgia, USA Email
MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing
随着数据密集型工作负载的不断增加，GPU作为最先进的单指令多线程（SIMT）处理器，受到内存带宽墙的阻碍。为了缓解这一瓶颈，先前提出的3D堆叠近库计算加速器通过使计算更接近DRAM库而受益于丰富的库内部带宽。然而，这些加速器专用于具有简单架构数据路径和定制软件映射方案的某些应用领域。对于通用场景，针对不同数据路径的轻量级硬件设计、对SIMT编程模型的架构支持以及端到端软件优化仍然具有挑战性。为了解决这些问题，我们提出了MPU（内存为中心的处理单元），第一个SIMT处理器的基础上3D堆叠近银行计算架构。首先，为了在利用库级带宽的同时以小的开销实现不同的数据路径，MPU采用了具有将指令卸载到近库计算逻辑的能力的混合流水线。其次，我们探讨了两个体系结构的SIMT编程模型，包括近银行共享内存设计和多个激活行缓冲区的增强支持。第三，我们提出了一个端到端的编译流程的MPU支持CUDA程序。为了充分利用MPU的混合流水线，我们开发了一个后端优化的指令卸载决策。在一组代表性的数据密集型工作负载上，MPU的评估结果显示，与NVIDIA Tesla V100 GPU相比，MPU的加速提高了3.46倍，能耗降低了2.57倍。
FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI
School of Intelligent Semiconductor Engineering, Chung-Ang University（智能半导体工程学院， Chung-Ang 大学）；AI Edge SoC Research Section, the Electronics and Telecommunications Research Institute（AI 边缘 SoC 研究部门，电子电信研究所）
CoroAMU: Unleashing Memory-Driven Coroutines through Latency-Aware Decoupled Operations
State Key Lab of Processors Institute of Computing Technology, Chinese Academy of Sciences（处理器重点实验室 中国科学院计算技术研究所）；University of Chinese Academy of Sciences（中国科学院大学）
DCC: Data-Centric Compilation of Machine Learning Kernels for Processing-In-Memory Architectures
University of Toronto（多伦多大学）；Vector Institute（向量研究所）；Barcelona Supercomputing Center（巴塞罗那超级计算中心）；ETH Zürich（苏黎世联邦理工学院）；Nvidia（英伟达）；Max Planck Institute for Software Systems（马克斯·普朗克软件系统研究所）
