以太网上的CXL：一种基于FPGA的数据中心存储拆分设计
CXL over Ethernet: A Novel FPGA-based Memory Disaggregation Design in Data Centers
摘要：
数据中心中的存储器资源通常遭受低利用率和缺乏动态性。内存分解通过解耦CPU和内存来解决这些问题，目前包括基于RDMA或互连协议（如Compute Express Link（CXL））的方法。然而，基于RDMA的方法涉及代码重构和更高的延迟。基于CXL的方法支持本地存储语义，克服了RDMA的缺点，但限于机架级。此外，基于CXL产品的内存池化和共享，目前还处于早期探索阶段，未来还需要时间才能面世。在本文中，我们提出了以太网上的CXL方法，主机处理器可以通过以太网访问远程存储器的内存语义。我们的方法可以支持本地内存加载/存储访问，并通过利用CXL和RDMA技术将物理范围扩展到跨服务器和机架级别。我们原型我们的方法与一个服务器和两个FPGA板与100 Gbps的网络和测量存储器访问延迟。此外，通过在关键路线中使用数据缓存和拥塞控制算法来优化存储器访问路径，进一步降低访问延迟。评测结果显示，服务器访问远程内存的平均延迟为1.97 μs，比业界基线延迟降低约37%。通过FPGA上的缓存块和命中访问，延迟可以进一步降低到415 ns。
英文摘要：
Memory resources in data centers generally suffer from low utilization and lack of dynamics. Memory disaggregation solves these problems by decoupling CPU and memory, which currently includes approaches based on RDMA or interconnection protocols such as Compute Express Link (CXL). However, the RDMA-based approach involves code refactoring and higher latency. The CXL-based approach supports native memory semantics and overcomes the shortcomings of RDMA, but is limited within rack level. In addition, memory pooling and sharing based on CXL products are currently in the process of early exploration and still take time to be available in the future. In this paper, we propose the CXL over Ethernet approach that the host processor can access the remote memory with memory semantics through Ethernet. Our approach can support native memory load/store access and extends the physical range to cross server and rack levels by taking advantage of CXL and RDMA technologies. We prototype our approach with one server and two FPGA boards with 100 Gbps network and measure the memory access latency. Furthermore, we optimize the memory access path by using data cache and congestion control algorithm in the critical path to further lower access latency. The evaluation results show that the average latency for the server to access remote memory is 1.97 μs, which is about 37% lower than the baseline latency in the industry. The latency can be further reduced to 415 ns with cache block and hit access on FPGA.
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