CXLMemSim：一种用于性能表征的纯软件模拟CXL.mem
CXLMemSim: A pure software simulated CXL.mem for performance characterization
AI总结：
本研究提出轻量级纯软件模拟框架CXLMemSim，通过内核探针等追踪内存访问并注入延迟模拟CXL.mem特性，在商用硬件上实现了比周期精确模拟器快数个数量级的准确性能表征，支持内存池相关技术的大规模评估。
摘要：
CXLMemSim是一个快速、轻量级的模拟框架，可用于对基于计算高速链路（Compute Express Link，CXL）.mem技术的内存系统进行性能表征。CXL.mem支持内存的分解与池化，以缓解云环境和数据中心环境中的内存搁浅问题（即被困在满载服务器上的内存未被充分利用）。然而，与本地DRAM相比，CXL连接的内存会带来额外的延迟和带宽限制，且真正的CXL.mem硬件目前尚未广泛普及，无法开展实证评估。\nCXLMemSim通过挂载到未修改的应用程序上、以软件方式模拟基于CXL的内存池，填补了这一空白。它的工作原理是利用高效的内核探针和硬件性能计数器追踪内存分配与访问，将执行过程划分为多个时间片，并注入时序延迟以模拟各类CXL.mem的延迟/带宽特性。这种方法在保留真实的加载/存储内存访问模式的同时，仅产生适中的运行时开销。\n我们在无需特殊设备的商用硬件上实现了CXLMemSim，评估结果表明，在处理真实工作负载时，它的运行速度比周期精确模拟器（如Gem5）快几个数量级，同时能准确建模CXL.mem对性能的影响。我们展示了多个用例：借助CXLMemSim，可以对内存池配置、调度策略、数据迁移策略和缓存技术开展实验，而这些此前都无法进行大规模评估。\n关键研究发现包括：低开销的基于软件的CXL.mem仿真具备可行性，揭示了内存池中的延迟和拥塞效应，还为系统设计人员优化内存分解提供了指导。总体而言，CXLMemSim为研究人员和从业者提供了一个实用且可扩展的平台，可在真实硬件普及之前探索CXL.mem的创新方向。
英文摘要：
CXLMemSim is a fast, lightweight simulation framework that enables performance characterization of memory systems based on Compute Express Link (CXL) .mem technology. CXL.mem allows disaggregation and pooling of memory to mitigate memory stranding (underutilized memory trapped on fully loaded servers) in cloud and datacenter environments. However, CXL-attached memory introduces additional latency and bandwidth constraints compared to local DRAM, and real CXL .mem hardware is not yet widely available for empirical evaluation. CXLMemSim addresses this gap by attaching to unmodified applications and simulating CXL-based memory pools in software. It operates by tracing memory allocations and accesses using efficient kernel probes and hardware performance counters, dividing execution into epochs, and injecting timing delays to emulate various CXL .mem latency/bandwidth characteristics. This approach incurs modest runtime overhead while preserving realistic load/store memory access patterns. We implement CXLMemSim on commodity hardware without special devices, and our evaluation shows that it runs orders of magnitude faster than cycle-accurate simulators (e.g., Gem5) for real-world workloads, while accurately modeling the performance impact of CXL .mem. We demonstrate use cases where CXLMemSim enables experimentation with memory pooling configurations, scheduling policies, data migration strategies, and caching techniques that were previously infeasible to evaluate at scale. Key findings include the viability of software-based CXL .mem emulation with low overhead, insights into latency and congestion effects in memory pools, and guidance for system designers to optimize memory disaggregation. Overall, CXLMemSim provides a practical and extensible platform for researchers and practitioners to explore CXL.mem innovations before real hardware becomes commonplace.
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