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arXiv 2103.06653cs.AR
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MPU:通过近库计算实现带宽丰富的SIMT处理器

MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing

Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie

摘要:

随着数据密集型工作负载的不断增加,GPU作为最先进的单指令多线程(SIMT)处理器,受到内存带宽墙的阻碍。为了缓解这一瓶颈,先前提出的3D堆叠近库计算加速器通过使计算更接近DRAM库而受益于丰富的库内部带宽。然而,这些加速器专用于具有简单架构数据路径和定制软件映射方案的某些应用领域。对于通用场景,针对不同数据路径的轻量级硬件设计、对SIMT编程模型的架构支持以及端到端软件优化仍然具有挑战性。为了解决这些问题,我们提出了MPU(内存为中心的处理单元),第一个SIMT处理器的基础上3D堆叠近银行计算架构。首先,为了在利用库级带宽的同时以小的开销实现不同的数据路径,MPU采用了具有将指令卸载到近库计算逻辑的能力的混合流水线。其次,我们探讨了两个体系结构的SIMT编程模型,包括近银行共享内存设计和多个激活行缓冲区的增强支持。第三,我们提出了一个端到端的编译流程的MPU支持CUDA程序。为了充分利用MPU的混合流水线,我们开发了一个后端优化的指令卸载决策。在一组代表性的数据密集型工作负载上,MPU的评估结果显示,与NVIDIA Tesla V100 GPU相比,MPU的加速提高了3.46倍,能耗降低了2.57倍。

英文摘要:

With the growing number of data-intensive workloads, GPU, which is the state-of-the-art single-instruction-multiple-thread (SIMT) processor, is hindered by the memory bandwidth wall. To alleviate this bottleneck, previously proposed 3D-stacking near-bank computing accelerators benefit from abundant bank-internal bandwidth by bringing computations closer to the DRAM banks. However, these accelerators are specialized for certain application domains with simple architecture data paths and customized software mapping schemes. For general purpose scenarios, lightweight hardware designs for diverse data paths, architectural supports for the SIMT programming model, and end-to-end software optimizations remain challenging. To address these issues, we propose MPU (Memory-centric Processing Unit), the first SIMT processor based on 3D-stacking near-bank computing architecture. First, to realize diverse data paths with small overheads while leveraging bank-level bandwidth, MPU adopts a hybrid pipeline with the capability of offloading instructions to near-bank compute-logic. Second, we explore two architectural supports for the SIMT programming model, including a near-bank shared memory design and a multiple activated row-buffers enhancement. Third, we present an end-to-end compilation flow for MPU to support CUDA programs. To fully utilize MPU's hybrid pipeline, we develop a backend optimization for the instruction offloading decision. The evaluation results of MPU demonstrate 3.46x speedup and 2.57x energy reduction compared with an NVIDIA Tesla V100 GPU on a set of representative data-intensive workloads.

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