Manticore：具有静态批量同步并行性的硬件加速RTL仿真
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
AI总结：
Manticore是一种利用静态批量同步并行模型加速RTL仿真的并行计算机，通过编译器调度消除同步开销，其225核FPGA实现优于最先进的RTL仿真器。
摘要：
摩尔定律和登纳德缩放定律的失效重新激发了人们对专用计算机架构和加速器的兴趣。这些硬件的验证和测试在很大程度上依赖于寄存器传输级（RTL）设计的周期精确仿真。最快的软件RTL仿真器可以以1-1000 kHz的速度仿真设计，即比硬件慢三个数量级以上。改进的仿真器可以通过加快设计迭代和允许更彻底的探索来提高设计者的生产力。一种可能性是利用低级并行性，因为RTL表达了大量的细粒度并发。不幸的是，最先进的RTL仿真器通常在单核上表现最佳，因为现代处理器无法有效利用细粒度并行性。本工作提出了Manticore：一种旨在加速RTL仿真的并行计算机。Manticore使用静态批量同步并行（BSP）执行模型来消除细粒度同步开销。它完全依赖编译器来调度资源和通信，这是可行的，因为RTL代码包含很少的分叉执行路径。通过静态调度，通信和同步不再产生运行时开销，使细粒度并行性变得实用。此外，静态调度极大地简化了处理器实现，显著增加了芯片上可容纳的核心数量。我们的225核FPGA实现以475 MHz运行，在9个基准测试中的8个中优于在桌面和服务器计算机上运行的最先进的RTL仿真器。
英文摘要：
The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The fastest software RTL simulators can simulate designs at 1--1000 kHz, i.e., more than three orders of magnitude slower than hardware. Improved simulators can increase designers' productivity by speeding design iterations and permitting more exhaustive exploration. One possibility is to exploit low-level parallelism, as RTL expresses considerable fine-grain concurrency. Unfortunately, state-of-the-art RTL simulators often perform best on a single core since modern processors cannot effectively exploit fine-grain parallelism. This work presents Manticore: a parallel computer designed to accelerate RTL simulation. Manticore uses a static bulk-synchronous parallel (BSP) execution model to eliminate fine-grain synchronization overhead. It relies entirely on a compiler to schedule resources and communication, which is feasible since RTL code contains few divergent execution paths. With static scheduling, communication and synchronization no longer incur runtime overhead, making fine-grain parallelism practical. Moreover, static scheduling dramatically simplifies processor implementation, significantly increasing the number of cores that fit on a chip. Our 225-core FPGA implementation running at 475 MHz outperforms a state-of-the-art RTL simulator running on desktop and server computers in 8 out of 9 benchmarks.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
